By: Jukka Larja (roskakori2006.delete@this.gmail.com), August 17, 2014 4:40 am
Room: Moderated Discussions
Aaron Spink (aaronspink.delete@this.notearthlink.net) on August 9, 2014 7:43 am wrote:
> juanrga (nospam.delete@this.juanrga.com) on August 9, 2014 5:57 am wrote:
> > X-Gene, Thunder-X, Vulcan... The most promising for me is Vulcan: eight-fetch and six-issue
> > per cycle, 60-entry unified scheduler, 180-Entry ROB, 2048-entry TLB, 64KB L1 (8-way),
> > 256KB L2 (8-way), 3 ALU, 256bit SIMD unit, SMT4, up to 16 cores on die, 3GHz...
> >
>
> Yes and I'm working on a 96 fetch, 64 issue, 60k-entry unified scheduler, 180k
> entry ROB, 2048M entry TLB, 64MB L1(80-way), 256GB L2 (8000-way), 30 alu, 2560bit
> SIMD unit, SMT4K, up to 32 thousand cores on die, 3Thz design....
This remainds me of a conversation from several years ago, here, between Lubemark and Richard Cownie:
"... on paper looked like a great chip (10 GFs at 1.2 GHZ whith 35W"
"It's a mystery to me why people continue to use silicon - processors on paper are always faster and cooler :-)"
-JLarja
> juanrga (nospam.delete@this.juanrga.com) on August 9, 2014 5:57 am wrote:
> > X-Gene, Thunder-X, Vulcan... The most promising for me is Vulcan: eight-fetch and six-issue
> > per cycle, 60-entry unified scheduler, 180-Entry ROB, 2048-entry TLB, 64KB L1 (8-way),
> > 256KB L2 (8-way), 3 ALU, 256bit SIMD unit, SMT4, up to 16 cores on die, 3GHz...
> >
>
> Yes and I'm working on a 96 fetch, 64 issue, 60k-entry unified scheduler, 180k
> entry ROB, 2048M entry TLB, 64MB L1(80-way), 256GB L2 (8000-way), 30 alu, 2560bit
> SIMD unit, SMT4K, up to 32 thousand cores on die, 3Thz design....
This remainds me of a conversation from several years ago, here, between Lubemark and Richard Cownie:
"... on paper looked like a great chip (10 GFs at 1.2 GHZ whith 35W"
"It's a mystery to me why people continue to use silicon - processors on paper are always faster and cooler :-)"
-JLarja