Klimax (danklima.delete@this.gmail.com) on August 17, 2014 10:42 pm wrote:
> Maynard Handley (name99.delete@this.name99.org) on August 17, 2014 4:10 pm wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on August 17, 2014 3:29 pm wrote:
> > > Maynard Handley (name99.delete@this.name99.org) on August 17, 2014 1:45 pm wrote:
> > > > Michael S (already5chosen.delete@this.yahoo.com) on August 17, 2014 1:15 pm wrote:
> > > > > Maynard Handley (name99.delete@this.name99.org) on August 17, 2014 12:37 pm wrote:
> > > > > > tarlinian (tarlinian.delete@this.gmail.com) on August 17, 2014 10:40 am wrote:
> > > > > > > Maynard Handley (name99.delete@this.name99.org) on August 17, 2014 10:06 am wrote:
> > > > > > > > Aaron Spink (aaronspink.delete@this.notearthlink.net) on August 16, 2014 9:10 pm wrote:
> > > > > > > > > juanrga (nospam.delete@this.juanrga.com) on August 16, 2014 2:56 am wrote:
> > > > > > > > > >
> > > > > > > > > > And a ~50% density advantage is not "a full node advantage" as I mentioned just
> > > > > > > > > > above. Intel _traditional_ process advantage has vanished, as others agree,
> > > > > > > > > >
> > > > > > > > > > http://www.electronicsweekly.com/news/components/microprocessors-and-dsps/whats-new-14nm-processors-intel-2014-08/
> > > > > > > > > >
> > > > > > > > > Lol, and if you believe that, I've got a couple bridges in the New York
> > > > > > > > > and San Francisco area codes for sale, cheap at twice the price!
> > > > > > > > >
> > > > > > > > > > TSMC claims _10nm_ risk production for late 2015. 16nm is being produced now (check above link). ARM server
> > > > > > > > > > 16nm parts will be available during 2015--2016. Broadwell has been delayed again to late 2015.
> > > > > > > > > >
> > > > > > > > > I don't believe that anyone in the industry has actually believed TSMC's public roadmaps
> > > > > > > > > for at least a decade. Here's my personal handy decoder ring for TSMC process speak:
> > > > > > > > >
> > > > > > > > > Risk Production = initial recipe, pretty much guaranteed not to work.
> > > > > > > > > Early Production = We think it might actually work now but like
> > > > > > > > > only every other wafer, give us at least another year or two
> > > > > > > > > Volume Production = We've almost hit what everyone calls risk production
> > > > > > > > > Mature Process = Early production
> > > > > > > > > Last generation process = Volume production!
> > > > > > > > > Obsolete process = Mature Process.
> > > > > > > > >
> > > > > > > > > If you keep this handy decoder ring in mind, then TSMC's process roadmap
> > > > > > > > > seems to make sense. Probably just an issue of things getting lost in translation
> > > > > > > > > somewhere between engineering speak, management speak, et al.
> > > > > > > > >
> > > > > > > >
> > > > > > > > I have zero experience with fabs. But as an outsider, one can hardly mock
> > > > > > > > TSMC for this when Intel appears to be doing the exact same thing.
> > > > > > > >
> > > > > > > > What exactly is the difference between Intel's "14nm is doing just fine, we'll have some
> > > > > > > > Broadwell-Y chips to sell you soon, and, BTW, the mass market 14nm Broadwells will come
> > > > > > > > out in July 2015" and Samsung or TSMC's "16nm is doing just fine, we'll have some specialty
> > > > > > > > chip to sell you soon, and, BTW, the mass market A9 will come out in Sept 2015"?
> > > > > > > >
> > > > > > >
> > > > > > > I would say Aaron exaggerates TSMC's marketing spin a bit, especially since there
> > > > > > > isn't anyone else who is obliged to attempt to market their manufacturing.
> > > > > > >
> > > > > > > Comparing low volume production for TSMC and Intel is a
> > > > > > > bit silly. You are aware that even Broadwell-Y alone
> > > > > > > is much more complex than the specialty chips we're talking
> > > > > > > about for TSMC (basically FPGAs running at maybe
> > > > > > > 1 kwspm?)? TSMC claimed volume production of 20 nm started in January and we've seen 1 rather low volume
> > > > > > > consumer product (Qualcomm 9x35 modem in a Korea only version of the S5 LTE-A version) on the market with
> > > > > > > chips from 20 nm. Admittedly this may be due to Apple buying most of their capacity, but Qualcomm's roadmap
> > > > > > > said that sampling of 20 nm SoCs would only begin in 2H 2014 with product shipments in 1H 2015.
> > > > > >
> > > > > > My point was more on the Intel side than the TSMC side. I cannot understand why no-one thinks
> > > > > > it absolutely BIZARRE that, in a process that is supposedly debugged and ready, Intel cannot
> > > > > > ship for six months/eleven months, the most desirable CPUs for that process
> > > > >
> > > > > Most desirable by whom? By Apply, which is ~5% of Intel's revenues or by 95%?
> > > > > I'd guess, 95% do not care about Broadwell laptop and desktop parts
> > > > > as long as they are not measurably cheaper than Haswell parts.
> > > > > On the other end, Broadwell-Y can be interesting to such important Intel OEM partners as Lenovo, ASUS,
> > > > > Toshiba, Dell, Samsung, LG. May be, even to HP and Acer, also this two giants appear more inert.
> > > > > It would also please Microsoft, which is *not* important OEM
> > > > > partner, but very important partner in other aspects.
> > > > >
> > > > > > and is, instead,
> > > > > > limiting itself to a novelty chip that is unlikely to sell in large quantities.
> > > > > > (Sure, maybe Intel knows something we don't, and the world
> > > > > > is soon going to be awash in devices that are clones
> > > > > > of either Surface Pro or Yoga, only with somewhat lower performance. But that strikes me as unlikely...)
> > > > > >
> > > > > > People seem quite happy to say that Intel's 14nm is "ready and running" without
> > > > > > accepting what this scheduling seems to be telling us about the true situation.
> > > > > >
> > > > >
> > > > > Most Intel's partners are in no hurry for 14nm.
> > > > > The only one that is real hurry is Altera. And even Altera will not lose much
> > > > > as long as Xilinx is late too. They will just not win as much as they hoped.
> > > >
> > > > This is the last post I will make on this subject because those involved keep changing the argument.
> > > > We have (as an apparent fact) that mainstream Broadwell is significantly delayed. So why?
> > >
> > > No, I think you just aren't piecing EVERYTHING together. You're seeing pieces, but not the whole.
> > >
> > > > If one argues that it's because Intel has hit the point where complexity is hurting
> > > > it in the Broadwell design, one is told no, the delay is because of the process.
> > >
> > > The delay was definitely due to 14nm yields. It's not a broadwell-specific issue.
> > >
> > > > If one argues that the process is unhealthy, one is told no, the delay is because OEMs
> > > > don't want the parts. (Unclear then, why they will want them more in 6/11 months?)
> > >
> > > The process was unhealthy. Now it's fine.
> > >
> > > > If one argues that the process then is not much of an advance on 22nm (since it's not resulting in parts
> > > > that are desirable) and so doesn't represent any real process advantage, one is told no, the problem is
> > > > that the Broadwell architecture is suboptimal, and it takes time to design a more optimal architecture.
> > > > And so we are back at the initial argument ---
> > >
> > > No, the issue is that the BDW architecture doesn't improve much for desktop. The CPU
> > > is about hte same speed, and IGPs aren't considered valuable for desktop. So 14nm is
> > > mostly valuable for mobile (and server). That's why Intel nixed socketed BDW.
> > >
> > > 14nm is an advantage over 22nm, but more in terms of power and performance at low power.
> > > I don't know if performance at maximum voltage will improve much. However, there should
> > > be an advantage at lower voltage levels. That helps the power sensitive guys the most
> > > (hypothetically, say frequency increases by 30% @ 0.7V and 10% at 1.0V).
> >
> > Think through what you are saying here, David.
> > The pattern since Nehalem has been that successive Intel CPUs are only about 5% faster than their
> > predecessor; the process (and micro-architecture) improvements have almost all gone into lower
> > power. Broadwell is not some strange deviation from the past, it is the natural extension of
> > this past. But you are claiming that this improvement balance is no longer desirable.
>
> Are you sure about Nehalem and Sandy Bridge? Because claim is wrong as written:
> http://techreport.com/review/20188/intel-sandy-bridge-core-processors
> (Just example, one could just include dozen of tests across time span to now to show miss)
>

I'm not sure which particular benchmark you expect is supposed to be the smoking gun in that article. But I would point out
(a) between Nehalem (2008) and Sandy Bridge (2011) was Westmere (2010). In other words, by my my, somewhat fuzzy but correct order of magnitude, reckoning, I'd expect an IPC improvement of about 10% between SB and Nehalem. This is an imperfect rule of thumb, not least because you can start arguing about EXACTLY which models are comparable, whether you should include higher frequencies at the same dollar point, or higher frequencies at the same thermals, whether you should aggressively (or not at all) weigh new instructions like AES and AVX, etc etc.

(b) The wikipedia page for SB
http://en.wikipedia.org/wiki/Sandy_Bridge_(microarchitecture)#Performance
agrees with this assessment: "The average performance increase, according to IXBT Labs and Semi Accurate as well as many other benchmarking sites, at clock to clock is 11.3% compared to the Nehalem Generation"

I'm not interested in scoring point here; I'm interested in understanding the performance characteristics of the underlying architecture for the most difficult type of code, ie the sort of branchy integer code that you see in compilers or web browsers. If you want to rip Wikipedia and IXBT Labs a new one, go right ahead; but my rule of thumb has been a pretty good indicator of what to expect (for the things *I* consider important) from each new Intel mainstream CPU since Westmere in 2010.

(c) This page of the article you reference:
http://techreport.com/review/20188/intel-sandy-bridge-core-processors/11
shows my point, IMHO. There are no clear winners for the SB micro-architecture, rather you get a mishmash ordering depending on the precise model and frequency of each micro-architecture. This is exactly what you would expect when the performance improvement of the new microarchitecture just is not that large compared to the previous microarchitecture.