nksingh (none.delete@this.none.non) on August 21, 2014 11:34 am wrote:
> > According to my understanding, the cheapest practical way to get effect of membar in
> > x86 WB memory region would be reading from the address of last write. Or, if you want
> > barrier after read (I never want, but I am not a lockless guy), writing to some dummy
> > locations that you are likely to own and then reading that location back.
>
> From my interpretation of the x86 memory model and your statement above, I think you won't
> get the ordering you desire. There's a squirrely exception in the x86 memory order model
> for store-buffer forwarding. In the version of the Software Dev Manual I have on hand, this
> behavior is spelled out in a section called "Intra-Processor Forwarding Is Allowed."
>

I will get ordering I desire, because I do not desire sequential consistency.
All I want is to get as strong effect as architecturally guaranteed by MFENCE instruction.

Pay attention that according to MEMORY ORDERING section of "Intel 64 and IA-32 Architectures
Software Developer’s Manual" MFENCE does not help total order at all. Locked instructions appear to be the only documented way to achieve it.