dmcq (dmcq.delete@this.fano.co.uk) on August 27, 2014 2:29 am wrote:
> Aaron Spink (aaronspink.delete@this.notearthlink.net) on August 26, 2014 5:27 pm wrote:
> > anon (anon.delete@this.anon.com) on August 26, 2014 6:06 am wrote:
> > > I had the idea from somewhere that LL/SC in POWER CPUs had similar kinds of hardware guarantees
> > > when used in very specific, limited sequences. That is, the hardware can take and hold the line
> > > to avoid livelocks, will avoid state transitions, etc. I don't have a reference off the top of
> > > my head (or the powerpc ISA manual handy to see what it says), so I could be wrong.
> > >
> > Basically all LL/SC architectures have put severe limits on the usage of LL/SC
> > to get them to actually work in practice. Lots of things like no stores between
> > LL/SC, limited number of instruction, limited number of loads, etcx.is done
>
> Yep they are a PITA as far as gdb and qemu are concerned as one has got to treat the complete sequence
> as a unit. It would always fail for instance if you just used gdb and executed a single instruction at
> a time. And on qemu with emulation it would always succeed if no special work to track the marker.

In fact I think I saw a bug a while ago in QEMU where they tried to generate an equivalent sequence of native instructions - but it had loads and stores of the emulated registers and that stopped it working properly!