By: anon (anon.delete@this.anon.com), August 28, 2014 10:45 pm
Room: Moderated Discussions
anon (anon.delete@this.anon.com) on August 28, 2014 8:25 pm wrote:
> But that might take you, spiritally, into CISC territory. Not that there is anything wrong
> with that for x86, or even prohibitive for a modern RISC, but it's a number of microcoded instructions
> that can be achieved with LL/SC.
BTW., I'm not saying that LL/SC themselves are *not* microcoded or that it is simple to implement on any modern RISC, but it's somewhat analogous to load/op/store vs load-op-store.
I just think LL/SC with restrictions is quite a decent RISCy solution for atomic RMW facility. Certainly nicer than LD/CAS for building low level operations. Although if it allowed for significant stream-lining of execution, then specialized atomic add/sub, dec&test-zero, and perhaps swap, and test&set bit, would be reasonable additions to an LL/SC ISA.
I guess the issue is that the cost of any atomic operation (and the often associated memory barriers) is high enough, and the relative frequency of atomic instructions low enough, that such specialized instructions are probably very high hanging fruit.
Impelmentations like POWER have traditionally spent more effort on making memory barriers more efficient, and reducing the underlying cost of atomic operations.
> But that might take you, spiritally, into CISC territory. Not that there is anything wrong
> with that for x86, or even prohibitive for a modern RISC, but it's a number of microcoded instructions
> that can be achieved with LL/SC.
BTW., I'm not saying that LL/SC themselves are *not* microcoded or that it is simple to implement on any modern RISC, but it's somewhat analogous to load/op/store vs load-op-store.
I just think LL/SC with restrictions is quite a decent RISCy solution for atomic RMW facility. Certainly nicer than LD/CAS for building low level operations. Although if it allowed for significant stream-lining of execution, then specialized atomic add/sub, dec&test-zero, and perhaps swap, and test&set bit, would be reasonable additions to an LL/SC ISA.
I guess the issue is that the cost of any atomic operation (and the often associated memory barriers) is high enough, and the relative frequency of atomic instructions low enough, that such specialized instructions are probably very high hanging fruit.
Impelmentations like POWER have traditionally spent more effort on making memory barriers more efficient, and reducing the underlying cost of atomic operations.
