rwessel (robertwessel.delete@this.yahoo.com) on August 29, 2014 1:14 am wrote:
> anon (anon.delete@this.anon.com) on August 28, 2014 8:25 pm wrote:
> > x86 does. x86 has a pretty decent range of RMW primitives - add/sub/xchg/cmpxchg/inc/dec
> > (where inc and dec also include ability to check for zero and such).
> >
> > But that might take you, spiritally, into CISC territory. Not that there is anything wrong
> > with that for x86, or even prohibitive for a modern RISC, but it's a number of microcoded instructions
> > that can be achieved with LL/SC. Although quite possibly in a more compact way that results
> > in less macro and micro instructions at least for common simple cases of inc/dec/etc. That
> > said, I would rather have atomic add/sub + LL/SC than have atomic add/sub + CAS.
> >
> > What else?
> >
> > SPARC has only CAS. zArch I know very little about but it seems to have only CAS.
> >
> > Are there other architectures which don't have LL/SC? Oh right, Itanium
> > yes? PARISC has some abomination called "load and clear word" only...
>
>
> zArch has a variety of CAS's (including a bunch under Perform Locked Operation), Test
> and Set (since the S/360 days), and now has a number of other atomic update instructions
> (Load and Add, for example).

Okay, thanks, yes I wasn't too sure of myself there.

> The current generation of hardware also supports transactional
> memory, which is another route to implementing many types of atomic update.

Yes certainly, also POWER and x86 (even though they weren't able to get it right yet).

But those are not yet (and maybe not ever) a good substitute for implementation of basic locks and counters. At least from measurement of x86 txn primitives. I would be surprised if POWER txn memory was equivalent speed to LL/SC. Don't know about z.