By: Linus Torvalds (torvalds.delete@this.linux-foundation.org), November 18, 2014 10:32 am
Room: Moderated Discussions
someone (someone.delete@this.somewhere.com) on November 17, 2014 8:10 pm wrote:
> >
> > The fact that should make you extra embarrassed for it is
> > that whole "Useful IPC counted using 'unstalled cycles'"
> > part, which takes the whole "let's inflate our CPI" to absolutely
> > ridiculous levels. You might even call it "lying",
> > since it has absolutely nothing to do with "CPI", and even less to do with the word "useful".
>
> That is interesting information related to available ILP in the compiled code, not an evil plot.
No it's not. And that's exactly what I'm arguing against. Christ, 'somebody', did you not even follow the whole argument?
The whole issue was exactly that people doing wide machines lie to themselves and others, by ignoring the fact that those wide machines also lose a lot of instructions when they stall. That was what this all started with, and it wasn't even me who made the argument, I just replied "Amen" to Patrick Chase.
And that Itanium paper is a perfect example of that kind of lying. It's talking up some theoretical IPC that has absolutely nothing to do with any reality, exactly by talking up the IPC and ignoring the costs of stalls.
In reality, Itanium had no greater IPC than anybody else. Anybody who in a paper talks about IPC values in the 2+ range is simply lying.
So give it up. You're the one who asked for examples from Intel or HP. I gave them to you. You're the one who cannot face reality here.
This is classic VLIW apologia, and exactly what I was talking about. And yes, EPIC made it worse by making the instruction packing (let's not call it IPC, because it damn well isn't, whatever the Intel and HP performance engineers said!) look better by using speculation.
Christ. Give it up. Why am I even responding to your crap?
The fact is, Itanium had bad performance, and had worse IPC than an out-of-order machine woudl have had. People who claim it had good IPC were either lying (and dammit, that Intel/HP paper really is at least "actively misleading" by calling it "CPI", if you think the "L" word is too harsh). Often by ignoring the costs of stalls. Exactly like in that paper!.
And when they weren't actively ignoring stalls and/or speculative instructions, they were ignoring the low frequency.
Linus
> >
> > The fact that should make you extra embarrassed for it is
> > that whole "Useful IPC counted using 'unstalled cycles'"
> > part, which takes the whole "let's inflate our CPI" to absolutely
> > ridiculous levels. You might even call it "lying",
> > since it has absolutely nothing to do with "CPI", and even less to do with the word "useful".
>
> That is interesting information related to available ILP in the compiled code, not an evil plot.
No it's not. And that's exactly what I'm arguing against. Christ, 'somebody', did you not even follow the whole argument?
The whole issue was exactly that people doing wide machines lie to themselves and others, by ignoring the fact that those wide machines also lose a lot of instructions when they stall. That was what this all started with, and it wasn't even me who made the argument, I just replied "Amen" to Patrick Chase.
And that Itanium paper is a perfect example of that kind of lying. It's talking up some theoretical IPC that has absolutely nothing to do with any reality, exactly by talking up the IPC and ignoring the costs of stalls.
In reality, Itanium had no greater IPC than anybody else. Anybody who in a paper talks about IPC values in the 2+ range is simply lying.
So give it up. You're the one who asked for examples from Intel or HP. I gave them to you. You're the one who cannot face reality here.
This is classic VLIW apologia, and exactly what I was talking about. And yes, EPIC made it worse by making the instruction packing (let's not call it IPC, because it damn well isn't, whatever the Intel and HP performance engineers said!) look better by using speculation.
Christ. Give it up. Why am I even responding to your crap?
The fact is, Itanium had bad performance, and had worse IPC than an out-of-order machine woudl have had. People who claim it had good IPC were either lying (and dammit, that Intel/HP paper really is at least "actively misleading" by calling it "CPI", if you think the "L" word is too harsh). Often by ignoring the costs of stalls. Exactly like in that paper!.
And when they weren't actively ignoring stalls and/or speculative instructions, they were ignoring the low frequency.
Linus