By: Michael S (already5chosen.delete@this.yahoo.com), November 23, 2014 11:24 am
Room: Moderated Discussions
Patrick Chase (patrickjchase.delete@this.gmail.com) on November 20, 2014 10:45 pm wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on November 20, 2014 12:10 pm wrote:
> > Patrick Chase (patrickjchase.delete@this.gmail.com) on November 20, 2014 11:30 am wrote:
> > > People love to be snarky about Intel and ISA complexity (and they certainly earned
> > > some of that with i432), but completely overlook that they somehow ended up with the
> > > one CISC ISA that was simple enough that modern micro-architectural techniques such
> > > as superscalar and OoO could be economically applied. VAX, m68k, etc all died out
> > > by the mid 80s due to overwhelming complexity.
> >
> > Well, both VAX and m68k lasted until early 90s.
>
> Yeah, that was a typo. I meant mid 90s.
>
> > If their owners were a little more
> > stubborn, they would have been lasted into 5M+ gates era where they again could
> > have become speed-competitive with x386. They missed it by just 3-4 years.
>
> I think it would have taken longer than that. VAX and its descendents (which includes m68k) were
> literally orthogonal to a fault, in the sense that every operand of an instruction could use
> any addressing mode available.
Thinking about it, I agree. It would take significantly more than 5M gates. However I don't agree that m68k was as bad as VAX. Even with all '020 cruft 68K was far easier. On the other hand, due to "vertical" business model, VAX could have afforded bigger die, lower yield, bigger power budget and wider external buses, so despite ISA inferiority it had potential of achieving competitive performance at about the same time as 68K.
> The "CISC penalty" for those makes x86 look like a party.
>
Apart of disadvantages, both 68K and VAX shared one advantage over x86 - 2-byte granularity of instructions. P6-style brute-force approach to parsing and early decoding would take relatively less hardware resources. I don't believe that it could have helped VAX, but it could make 3-way 68K feasible even in transistor budget that does not allow decent decoded instruction cache.
> Michael S (already5chosen.delete@this.yahoo.com) on November 20, 2014 12:10 pm wrote:
> > Patrick Chase (patrickjchase.delete@this.gmail.com) on November 20, 2014 11:30 am wrote:
> > > People love to be snarky about Intel and ISA complexity (and they certainly earned
> > > some of that with i432), but completely overlook that they somehow ended up with the
> > > one CISC ISA that was simple enough that modern micro-architectural techniques such
> > > as superscalar and OoO could be economically applied. VAX, m68k, etc all died out
> > > by the mid 80s due to overwhelming complexity.
> >
> > Well, both VAX and m68k lasted until early 90s.
>
> Yeah, that was a typo. I meant mid 90s.
>
> > If their owners were a little more
> > stubborn, they would have been lasted into 5M+ gates era where they again could
> > have become speed-competitive with x386. They missed it by just 3-4 years.
>
> I think it would have taken longer than that. VAX and its descendents (which includes m68k) were
> literally orthogonal to a fault, in the sense that every operand of an instruction could use
> any addressing mode available.
Thinking about it, I agree. It would take significantly more than 5M gates. However I don't agree that m68k was as bad as VAX. Even with all '020 cruft 68K was far easier. On the other hand, due to "vertical" business model, VAX could have afforded bigger die, lower yield, bigger power budget and wider external buses, so despite ISA inferiority it had potential of achieving competitive performance at about the same time as 68K.
> The "CISC penalty" for those makes x86 look like a party.
>
Apart of disadvantages, both 68K and VAX shared one advantage over x86 - 2-byte granularity of instructions. P6-style brute-force approach to parsing and early decoding would take relatively less hardware resources. I don't believe that it could have helped VAX, but it could make 3-way 68K feasible even in transistor budget that does not allow decent decoded instruction cache.
