By: Terry A Gray (cuyahogan.delete@this.aol.com), November 23, 2014 3:42 pm
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on November 23, 2014 11:24 am wrote:
Clip.
> Apart of disadvantages, both 68K and VAX shared one advantage over x86 - 2-byte granularity of
> instructions. P6-style brute-force approach to parsing and early decoding would take relatively
> less hardware resources. I don't believe that it could have helped VAX, but it could make 3-way
> 68K feasible even in transistor budget that does not allow decent decoded instruction cache.
>
Probably going off on a tangent on this thread.
I have long felt that DEC (and many other makers of 16 bit systems) made an error when the PDP-11 was designed as 16 bit. If they had stuck with 18 bit as in the PDP-15 line and its predecessors it would have allowed 2 bits for size instead of 1 and an extra bit for OP Codes. This would have gone against the 8 bit byte but would have allowed 9, 18, 36, and 72 bit registers. The extra 2 bits of address in the original 18 bit version would have allowed 4 times the memory. I have seen quotes that DEC was embarrassed that they had to add memory management so soon to access larger memory and that they had used too much of the OP Code space. This could have easily been expanded to 36 and 72 bit computers without changing the initial ISA OP Codes. This seems to be a historical advantage as both x86 and IBM-360 show. Seems INTEL has failed every time they have tried to switch to a completely different ISA/OP Code set.
I think of this as the computer inertia factor.
Terry A Gray - Old Machine Language Programmer
Clip.
> Apart of disadvantages, both 68K and VAX shared one advantage over x86 - 2-byte granularity of
> instructions. P6-style brute-force approach to parsing and early decoding would take relatively
> less hardware resources. I don't believe that it could have helped VAX, but it could make 3-way
> 68K feasible even in transistor budget that does not allow decent decoded instruction cache.
>
Probably going off on a tangent on this thread.
I have long felt that DEC (and many other makers of 16 bit systems) made an error when the PDP-11 was designed as 16 bit. If they had stuck with 18 bit as in the PDP-15 line and its predecessors it would have allowed 2 bits for size instead of 1 and an extra bit for OP Codes. This would have gone against the 8 bit byte but would have allowed 9, 18, 36, and 72 bit registers. The extra 2 bits of address in the original 18 bit version would have allowed 4 times the memory. I have seen quotes that DEC was embarrassed that they had to add memory management so soon to access larger memory and that they had used too much of the OP Code space. This could have easily been expanded to 36 and 72 bit computers without changing the initial ISA OP Codes. This seems to be a historical advantage as both x86 and IBM-360 show. Seems INTEL has failed every time they have tried to switch to a completely different ISA/OP Code set.
I think of this as the computer inertia factor.
Terry A Gray - Old Machine Language Programmer