Make RISCY case fast CISCY case slow implementation

By: Jouni Osmala (josmala.delete@this.cc.hut.fi), November 30, 2014 3:08 am
Room: Moderated Discussions
Ronald Maas (rmaas.delete@this.wiwo.nl) on November 29, 2014 9:58 am wrote:
> Jouni Osmala (josmala.delete@this.cc.hut.fi) on November 25, 2014 4:40 am wrote:
> > Ronald Maas (rmaas.delete@this.wiwo.nl) on November 24, 2014 7:13 pm wrote:
> > > Michael S (already5chosen.delete@this.yahoo.com) on November 23, 2014 11:24 am wrote:
> > > > Apart of disadvantages, both 68K and VAX shared one advantage over x86 - 2-byte granularity of
> > > > instructions. P6-style brute-force approach to parsing and early decoding would take relatively
> > > > less hardware resources. I don't believe that it could have helped VAX, but it could make 3-way
> > > > 68K feasible even in transistor budget that does not allow decent decoded instruction cache.
> > > >
> > > >
> > >
> > > A huge benefit of the x86 instruction encoding scheme is
> > > that it allows determination of the instruction length
> > > by inspecting only the first 1, 2 or 3 bytes of the instruction
> > > (not counting any prefixes). The only exception
> > > is when some length-changing prefixes are used such as
> > > address size prefix and operand size prefix. When the
> > > processor encounters these prefixes in the instruction streams, it is not able to decode these instructions
> > > in a single cycle anymore. Search for LCP in the Intel Optimization Reference Manual http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
> > >
> > > With 68K and VAX often the whole instruction must be parsed in order to determine its length. Which would
> > > significantly increase the technical complexity required for building a superscalar instruction decoder.
> > >
> > > Just to illustrate here a fragment from a document "Another
> > > Approach to Instruction Set Architecture — VAX" :
> > >
> > > How long is the following instruction?
> > >
> > > addl3 r1, 737(r2), (r3)[r4]
> > >
> > > The name addl3 means a 32-bit add instruction with three operands. Assume the length of the VAX opcode is 1
> > > byte. The first operand specifier — r1 — indicates register
> > > addressing and is 1 byte long. The second operand
> > > specifier — 737(r2) — indicates displacement addressing
> > > and has two parts: the first part is a byte that
> > > specifies the word-displacement addressing mode and base register
> > > (r2); the second part is the 2-byte long displacement
> > > (737). The third operand specifier — (r3)[r4] — also has
> > > two parts: the first byte specifies register deferred
> > > addressing mode ((r3)), and the second byte specifies the
> > > Index register and the use of indexed addressing ([r4]).
> > > Thus, the total length of the instruction is 1 + (1) + (1+2) + (1+1) = 7 bytes.
> > >
> > > Ronald
> >
> > Think about all instructions that would in PPRO be SINGLE uop how complicated
> > is THEIR length calculation in VAX? Remember PPRO didn't handle more than 1 complex
> > and less than 1 really complex instructions per cycle in front end.
> >
> > So simple,simple,complex, combo wouldn't be harder in vax than x86. And then the
> > lets stall the front end to handle REALLY complex instruction from microcode case
> > that pentium pro had, and there is no reason why VAX couldn't make same choice.
> >
> > I think following could be what parallel vax decoder would of looked for era after
> > VAX was cancelled, and its similar to what X86 does but modified for VAX:s orthogonality.
> > Most of the work could be moved to instruction cache fill.
> >
> > -------------------
> > Lets assume every byte is a addressing mode specifier and decode that.
> > Lets assume every byte(pair) is instruction opcode decode that.
> > ---------------------
> > Go through dependency tree from first instruction to last
> > to pick which uops to put forward, Counting operands
> > and going forward amount of bytes specified by decoded addressing mode specifier. Register specifiers are
> > collapsed to opcode directly, memory operands write temporary register and are separate uop.
> > ---------------------------------------------
> > Handling the case in which front end produces too many uops for scheduler to take in a cycle. Forward
> > the operand getting operands from memory uops, keep the instruction opcode waiting for additional
> > operands if instruction splits to next fetch waiting for additional operands to finish.
> > And going for micro code for really complex cases.
> > --------------------------------------------------
> So if I understand you correctly, you want to decode each part of the instruction in separate decoders parallelly.
> E.g. 1 decoder for opcode, 2nd decoder for operand specifier 1, 3rd decoder for operand specifier 2.
>
> Any thoughts how many decoders would be needed to approach the performance of PPro? Then
> do you want to have decoders that can only decode opcodes or operand specifiers, or decoders that can do both.

I think splitting both to bunch of smaller decoders makes overall decoder smaller and simpler, but both actually depend on lots of details on actual encoding which would require reading all the nifty details of encoding and doing bunch of analysis. Only someone who has actually done VAX decoder could answer that definitely without too much work.

I'm thinking splitting it to bunch of smaller decoders could handle about 8-16 bytes of code about similar transistor cost to a hardware multiplier.

If both then one decoder per byte of fetch, 16 bytes so 16 decoders. I take 16 from the amount I cache fetch pentium PRO had, assuming VAX would need to match that to compete. 8 maybe close to pentium PRO, it would really require more detailed analysis than its worth, if 8 would be enough because of buffering in the OoO back end, and better code density.

But just remember each one pentium PRO:s decoders for software where bundle of hardware decoders and not just one so we really cannot compare their count, only realize both are complex and large piece of hardware.


>Note that the operand specifiers per VAX instruction can vary from
> 0 to 6 according to http://www.cs.ccsu.edu/~kjell/cs254/ch08/ch8_11.html

I knew that and that's why decoders need to be byte oriented instead of instruction oriented. But maximum count maybe restricted in parallel decoder, compared to microcode decoder, if it would make it faster and simpler. You need either 2 bit counter or 3 bitlines to count if doing only simple cases with parallel decoder.

> By the way, I do think it makes sense to do it the way you suggested.
>
> Ronald

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                                                                  There he goes again on his favorite hobby horseLinus Torvalds2014/11/16 05:17 PM
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                                                                                    There he goes again on his favorite hobby horsegallier22014/11/18 01:55 AM
                                                                              There he goes again on his favorite hobby horseAaron Spink2014/11/19 10:22 AM
                                                                                There he goes again on his favorite hobby horseMaynard Handley2014/11/19 10:31 AM
                                                                                  There he goes again on his favorite hobby horseAaron Spink2014/11/20 09:33 AM
                                                                                    There he goes again on his favorite hobby horseMichael S2014/11/20 10:14 AM
                                                                                      There he goes again on his favorite hobby horsePatrick Chase2014/11/20 11:30 AM
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                                                                                          There he goes again on his favorite hobby horseMichael S2014/11/20 12:23 PM
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                                                                                              What I hope is only a slight tangentTerry A Gray2014/11/23 03:42 PM
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                                                                                                VAX could HAVE made it...gallier22014/11/24 08:26 AM
                                                                                                John Mashey has a comp.arch post that is relevant (maybe)Mark Roulo2014/11/24 04:17 PM
                                                                                                  John Mashey has a comp.arch post that is relevant (maybe)Mark Rouo2014/11/24 04:21 PM
                                                                                                  John Mashey has a comp.arch post that is relevant (maybe)Linus Torvalds2014/11/24 06:17 PM
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                                                                                                    Another bump in complexity...David Kanter2014/11/25 11:02 AM
                                                                                                      Another bump in complexity...Peter Lund2014/11/27 12:51 PM
                                                                                                    John Mashey has a comp.arch post that is relevant (maybe)Ricardo B2014/11/25 04:34 PM
                                                                                                      John Mashey has a comp.arch post that is relevant (maybe)Peter Lund2014/11/27 12:48 PM
                                                                                                        John Mashey has a comp.arch post that is relevant (maybe)Peter Lund2014/11/27 12:56 PM
                                                                                                        John Mashey has a comp.arch post that is relevant (maybe)Ricardo B2014/11/27 04:04 PM
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                                                                                                    There he goes again on his favorite hobby horserwessel2014/11/28 01:52 AM
                                                                                                    68k line decoding and opcodesBrett2014/11/28 10:42 AM
                                                                                                    There he goes again on his favorite hobby horsePatrick Chase2014/11/28 04:42 PM
                                                                                                      Yet another form of "worse is better" ? (NT)Michael S2014/11/29 12:12 PM
                                                                                                        Yet another form of "worse is better" ?Patrick Chase2014/11/30 07:23 PM
                                                                                                          Yet another form of "worse is better" ?dmcq2014/12/01 02:08 AM
                                                                                                            Yet another form of "worse is better" ?Jouni Osmala2014/12/01 11:19 PM
                                                                                                              Yet another form of "worse is better" ?Patrick Chase2014/12/02 01:54 PM
                                                                                                                Yet another form of "worse is better" ?Stunk2014/12/03 01:45 PM
                                                                                                Make RISCY case fast CISCY case slow implementationJouni Osmala2014/11/25 04:40 AM
                                                                                                  Make RISCY case fast CISCY case slow implementationPeter Lund2014/11/27 01:13 PM
                                                                                                  Make RISCY case fast CISCY case slow implementationRonald Maas2014/11/29 09:58 AM
                                                                                                    Make RISCY case fast CISCY case slow implementationJouni Osmala2014/11/30 03:08 AM
                                                                                                There he goes again on his favorite hobby horsePeter Lund2014/11/27 01:03 PM
                                                                                    There he goes again on his favorite hobby horseMaynard Handley2014/11/20 11:13 AM
                                                                                      There he goes again on his favorite hobby horsePatrick Chase2014/11/20 11:34 AM
                                                                                      There he goes again on his favorite hobby horsePatrick Chase2014/11/20 10:39 PM
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                                                                                          There he goes again on his favorite hobby horsePatrick Chase2014/11/21 10:33 AM
                                                                                        There he goes again on his favorite hobby horseMichael S2014/11/21 03:49 AM
                                                                                          GPRs did rotate, renaming not in execute critical loopPaul A. Clayton2014/11/21 05:29 AM
                                                                                            GPRs did rotate, renaming not in execute critical loopLinus Torvalds2014/11/21 10:14 AM
                                                                                Information on Intel pre-Itanium architecture effort?Mark Roulo2014/11/19 11:17 AM
                                                                                  Information on Intel pre-Itanium architecture effort?Kira2014/11/20 07:35 AM
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                                                                          There he goes again on his favorite hobby horseMaynard Handley2014/11/17 04:14 PM
                                                                            There he goes again on his favorite hobby horseDoug S2014/11/17 10:52 PM
                                                                          There he goes again on his favorite hobby horsecoppice2014/11/17 08:11 PM
                                                                    There he goes again on his favorite hobby horsesomeone2014/11/17 07:20 AM
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                                                            How many CPU cores?Michael S2014/12/10 02:10 AM
                                                              How many CPU cores?Gabriele Svelto2014/12/10 07:07 AM
                                                          How many CPU cores?Konrad Schwarz2014/12/10 09:23 AM
                                      The x86 core is Zenjuanrga2014/11/09 06:44 AM
                                        The x86 core is Zendmcq2014/11/16 05:09 AM
                              But can it beat an optimized OoO?Ken H2014/11/02 09:54 PM
                                But can it beat an optimized OoO?Michael S2014/11/03 12:29 AM
                                But can it beat an optimized OoO?Heikki Kultala2014/11/04 05:01 AM
                                  Bulldozer design 'stupidity'Paul A. Clayton2014/11/04 09:16 AM
                                    Bulldozer design 'stupidity'juanrga2014/11/04 12:14 PM
                                    Bulldozer design 'stupidity'h2014/11/04 01:14 PM
                                      Bulldozer module as drop-in macro?Paul A. Clayton2014/11/04 01:26 PM
                                      Bulldozer L2 latency(re: Bulldozer design 'stupidity')Heikki Kultala2014/11/16 11:12 PM
                                        Bulldozer L2 latency(re: Bulldozer design 'stupidity')Y2014/11/18 10:06 AM
                                  But can it beat an optimized OoO?juanrga2014/11/04 12:18 PM
                                But can it beat an optimized OoO?Exophase2014/11/09 08:01 PM
                      Soft Machines Inventionsook2014/10/29 09:20 AM
  Soft MachinesGabriele Svelto2014/10/23 02:09 PM
    Soft MachinesMaynard Handley2014/10/23 02:29 PM
    Soft Machinesex-apple2014/10/23 02:32 PM
      Soft MachinesSteve2014/10/24 09:37 AM
        How well does Soft Machines do on ARM/x86?ex-apple2014/10/24 12:08 PM
          How well does Soft Machines do on ARM/x86?mpx2014/10/25 04:37 AM
            How well does Soft Machines do on ARM/x86?none2014/10/25 02:15 PM
              jazelleHeikki Kultala2014/10/26 12:18 AM
      Soft MachinesPatrick Chase2014/10/24 01:27 PM
        Soft Machinesjuanrga2014/10/25 02:34 AM
          Soft MachinesPatrick Chase2014/10/28 10:59 AM
    Soft MachinesKira2014/10/23 02:48 PM
      SemiAccurate on Soft Machinesex-apple2014/10/23 05:17 PM
        SemiAccurate on Soft MachinesBrendan2014/10/24 12:49 AM
        SemiAccurate on Soft Machinesdmcq2014/10/24 03:55 AM
        Are they on 28 nm?Kevin G2014/10/26 04:23 PM
          Are they on 28 nm?ex-apple2014/10/26 04:47 PM
      Soft Machinessomeone2014/10/24 08:53 AM
    pipeline lengthHeikki Kultala2014/10/24 12:50 AM
  Soft MachinesKira2014/10/23 02:31 PM
  Soft Machinesjust some guy2014/10/24 04:50 AM
    Soft MachinesMr. Camel2014/10/24 10:16 AM
  Soft Machines investorsMichael S2014/10/25 11:06 AM
    Why? (NT)Megol2014/10/25 12:46 PM
    Soft Machines investor backstoryex-apple2014/10/28 09:30 PM
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