Konrad Schwarz (no.spam.delete@this.no.spam) on December 4, 2014 1:10 pm wrote:

> > This actually brings me to an architecture area that is of interest to me: Pretty much all architectures
> > are still completely cache unaware. Most of out coherency primitives and their functions are designed with
> > willful ignorance of the concept of caches. Basically all load store ops are still designed around a model
> > where everything is directly connected to a shared bus without caches. Given the modern reality and the
> > likelihood of it going forward, there is a lot of optimization
> > space available around making the whole load/store
> > ISA space much more cache aware going directly back into the actual
>
> I think the Cell SPE showed that more complex memory models are unpalatable to programmers.
>

No, CELL SPE simply showed that a broken lack of memory models are unpalatable to programmers. The whole, we'll give you a data store basically the same size as most peoples cache and then force you to use DMA to get anything in or out of it.