By: Ungo (a.delete@this.b.c.d.e), January 4, 2015 3:27 pm
Room: Moderated Discussions
Troll? (trashbin67.delete@this.gmail.com) on January 2, 2015 7:55 am wrote:
> I won't disagree with the statement, but there is something to be said for parallelizing via specialized cores
> vice GP ones. We already have things like hardware MPEG decoders and DSPs on mobile devices, GPUs for graphics,
> and appliance crypto, and the price/perf/power ratios seem to come out well. Why not have a standard block
> of 20 or 50 or however many ASICs on-die with 4-6 GP-CPUs, and let the OS decide how to parcel out tasks?
Current mainstream x86 CPUs have GP CPU cores, an integrated GPU, and hardware accelerator blocks for functions like MPEG4 encode/decode, cryptography, etc. Not sure what you're asking for that isn't already being done.
> I
> don't know where FPGA technology stands, but I'm guessing it loses on power.
To ASIC in the same process node? Yes. By a lot. FPGA also loses on the die area needed to implement any given functional block, and clock speed. Such is the cost of reconfigurability.
> I won't disagree with the statement, but there is something to be said for parallelizing via specialized cores
> vice GP ones. We already have things like hardware MPEG decoders and DSPs on mobile devices, GPUs for graphics,
> and appliance crypto, and the price/perf/power ratios seem to come out well. Why not have a standard block
> of 20 or 50 or however many ASICs on-die with 4-6 GP-CPUs, and let the OS decide how to parcel out tasks?
Current mainstream x86 CPUs have GP CPU cores, an integrated GPU, and hardware accelerator blocks for functions like MPEG4 encode/decode, cryptography, etc. Not sure what you're asking for that isn't already being done.
> I
> don't know where FPGA technology stands, but I'm guessing it loses on power.
To ASIC in the same process node? Yes. By a lot. FPGA also loses on the die area needed to implement any given functional block, and clock speed. Such is the cost of reconfigurability.