By: Eric Bron (eric.bron.delete@this.zvisuel.privatefortest.com), January 9, 2015 3:30 pm
Room: Moderated Discussions
> I have to admit that I was surprised at how well OoO did in
> such a throughput-oriented set of benchmarks, though :-).
moreover this is without using a SIMD ISA, if I understand it well from Performance Modeling (p. 298)
"Each core has private L1 instruction and data caches, a single-precision floating point unit, and a MIPS-like RISC instruction set."
> such a throughput-oriented set of benchmarks, though :-).
moreover this is without using a SIMD ISA, if I understand it well from Performance Modeling (p. 298)
"Each core has private L1 instruction and data caches, a single-precision floating point unit, and a MIPS-like RISC instruction set."