Aaron Spink (aaronspink.delete@this.notearthlink.net) on January 11, 2015 5:55 pm wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on January 11, 2015 5:44 am wrote:
> > Do you count Maxwell SMM as single core?
> > I think, it's more reasonable to count it as quad-core module. It would be more consistent
> > with what we consider "a core" in traditional or semi-traditional (Bulldozer) CPUs.
> >
>
> Yes, an SMM is a single core. And I count it as a single core because Nvidia considers it
> a single core. If they thought it was a 4 core cluster than they would of either renamed it
> or made each sub-block a different SMM.

I think, what they name it is pretty irrelevant. You don't follow their nomenclature when they call SIMD lane "CUDA core", do you?

> The Maxwell SMM basically goes from having a global
> scheduler to having 4 sub schedulers with dedicated resources. That doesn't mean they are
> 4 cores unless you want to consider most current cpu cores as containing multiple cores.
>

To me quarter-SMM looks very similar to single multithreaded CPU core. Much more so than full SMM.

>
> > What is your threshold? Mine is 50.
> >
>
> at 22/14nm? >100 and a hardware programming model dependent on function shipping. You
> know, the whole thing that manycore was founded on.

In fact, I don't know. Can you elaborate?

> The whole idea of having a line
> between manycore and multicore based solely on core count is basically bunk. Manycore
> has several actual structural hardware requirements beyond just lots of cores.
>

I will be very interested to know what are those requirements. To me "manycore" does not sound like firmly established term.

>
> > The integer part is most likely OoO, but I am not expecting VPU ALUs to be OoO.
> > As far as I am concerned, the most intriguing uArch question about KNL is if VPU loads can be
> > issued ahead of preceding VPU ALU and VPU store operations and if yes then to which degree.
> >
>
> I would bet money that whatever the FPU on silvermont does is what the VPU on the KNL will do.
>

I am not sure. The amount of software-visible vector registers on KNL is a lot higher than the amount of software-visible x87+SSE registers on Silvermont. That's especially true if KNL has SMT, which is likely, but true even without SMT. So, register renaming will be both less necessary and more costly.

But if you are correct than KNL will be capable to promote VPU loads ahead of VPU ALU ops, but not ahead of VPU stores.