By: Eric Bron (eric.bron.delete@this.zvisuel.privatefortest.com), January 12, 2015 6:29 am
Room: Moderated Discussions
> I am not sure. The amount of software-visible vector registers on KNL is a lot higher than the amount
> of software-visible x87+SSE registers on Silvermont. That's especially true if KNL has SMT, which is likely,
from slide 13 of [1] we know that enhancements vs. Silvermont will include:
1) 3x peak FLOPS per core
2) deep OoO buffers
3) 4 hardware threads per core
(1) confirm 2 VPUs per core as in the laked slides (assuming 1.5 x frequency)
(2) and (3) makes one think that SMT is very likely, i.e. it will be able to issue the same clock two AVX-512 instructions from 2 different threads
[1]
Knights Corner: Your Path to Knights Landing
> of software-visible x87+SSE registers on Silvermont. That's especially true if KNL has SMT, which is likely,
from slide 13 of [1] we know that enhancements vs. Silvermont will include:
1) 3x peak FLOPS per core
2) deep OoO buffers
3) 4 hardware threads per core
(1) confirm 2 VPUs per core as in the laked slides (assuming 1.5 x frequency)
(2) and (3) makes one think that SMT is very likely, i.e. it will be able to issue the same clock two AVX-512 instructions from 2 different threads
[1]
Knights Corner: Your Path to Knights Landing