Ronald Maas (rmaas.delete@this.wiwo.nl) on February 3, 2015 8:23 pm wrote:
> Hugo Décharnes (hdecharn.delete@this.outlook.fr) on February 3, 2015 2:20 pm wrote:
> > Cortex-A57 delivers better performances than Cortex-A15, though their micro-architectures
> > are–nearly–identical. We'll see if ARM Ltd. reiterates with Cortex-A72.
>
> ARM's own web page about Cortex-A72 mentions 'major micro-architectural improvements'. This
> implies that the micro-architecture will be different compared to the Cortex-A15/A57.
>
> So guys. Any ideas what ARM could have do to make such an impressive performance
> improvement compared to A57? My pick (entirely speculative of cause):
>
> - 4 instruction decoder

Would its IPC actually warrant a 4 wide decoder yet? Such a thing should not improve energy efficiency.

> - memory disambiguation

Memory disambiguation also does not seem like it would improve efficiency much. It increases the amount of speculation that can be done, which can increase performance of course, but improve perf/watt? I think IBM only implemented this with POWER8, and they haven't been ones to shy away from micro architectural complexity.

I would say perhaps improved branch prediction, reorganized cache design, and improved hardware prefetching.

I think the L2 cache might be brought in and be integrated with the core design as it is with other high performance CPUs. With a more modular and configurable L3 cache shared within the cluster. The low associativity L1 and large shared modular L2 seems like a potential problem to me.

> - 2 x 128-bit NEON execution units
>
> Ronald