Seni (seniike.delete@this.hotmail.com) on February 4, 2015 1:33 pm wrote:
> Maynard Handley (name99.delete@this.name99.org) on February 4, 2015 11:42 am wrote:
> > Seni (seniike.delete@this.hotmail.com) on February 4, 2015 1:19 am wrote:
> > > Ronald Maas (rmaas.delete@this.wiwo.nl) on February 3, 2015 8:23 pm wrote:
> > > > Hugo Décharnes (hdecharn.delete@this.outlook.fr) on February 3, 2015 2:20 pm wrote:
> > > > > Cortex-A57 delivers better performances than Cortex-A15, though their micro-architectures
> > > > > are–nearly–identical. We'll see if ARM Ltd. reiterates with Cortex-A72.
> > > >
> > > > ARM's own web page about Cortex-A72 mentions 'major micro-architectural improvements'. This
> > > > implies that the micro-architecture will be different compared to the Cortex-A15/A57.
> > > >
> > > > So guys. Any ideas what ARM could have do to make such an impressive performance
> > > > improvement compared to A57? My pick (entirely speculative of cause):
> > > >
> > > > - 4 instruction decoder
> > > > - memory disambiguation
> > > > - 2 x 128-bit NEON execution units
> > > >
> > > > Ronald
> > >
> > > Most likely:
> > >
> > > - repipelined for ~30% higher frequency target
> > > - more simd
> > > - wider memory bus
> > > - nothing else
> >
> > You don't think they'll at least add the ARMv8.1 RMW atomics? (Not that that changes performance
> > substantially, but I imagine they want that part of the ISA to be universalized ASAP.)
>
> If they did, it wouldn't count as a major microarchitectural improvement,
> because it's not microarchitectural at all. It's just architectural.

I'd have thought they would want to make changes to the interconnect to deal with the atomics efficiently rather than implementing them wholly within the processor building on top of the current way of dealing with such things. Which might explain why they haven't bothered to stick it into the Cortex-A72.