ARM announces A72 (fixed format)

By: anon (, February 4, 2015 11:29 pm
Room: Moderated Discussions
anon ( on February 4, 2015 11:27 pm wrote:
> Exophase ( on February 4, 2015 2:33 pm wrote:
> > David Kanter ( on February 4, 2015 11:25 am wrote:
> > > Memory disambiguation would be most useful with another load unit.
> > >
> > > I would do another load unit. I don't think it's very helpful to do 2 ST/clock,
> > > especially since it makes your store buffer a lot nastier to deal with.
> > >
> >
> > I don't think it's a coincidence that Core 2 both increased width across the board and added memory
> > disambiguation, all while not adding a second store port until two uarch generations later. Although
> > I do of course agree that disambiguation would be more effective with a second load port.
> >
> > I have written lots of code which has a higher than 1:2 load to ALU density for decent sized chunks or loop
> > bodies, so I do think a second load unit would help a lot. Even more so if they're adding a third ALU.
> Silvermont does not do memory disambiguation, despite Intel having perhaps more experience than
> anyone with it. Although it is their first gen core, so it's possible they decided to limited
> some complexities. It does suggest that it's not the lowest hanging of fruit, though.
> >
> > > Prefetching and branch prediction will probably improve.
> > >
> >
> > From what I could gather in the TRMs, the prefetching to date seems to be based on observing
> > access patterns in the cache (originally, from cache misses). I don't know if they've moved
> > beyond this already, but if not they'd benefit from having IP-hashed stream detection.
> >
> > > And yes, hopefully they will fix their cache design...but I think a lot of that
> > > is tied to the PD capabilities of clients (which is to say, not much).
> > >
> >
> > When you say fix it, are you referring to latencies, size, hierarchy arrangement,
> > or what? Size and hierarchy arrangement are really pretty much the same as
> > everyone else in these segments, unless you count Broadwell-Y.

Fixed format:

L1I L1D L2
A15 (Exynos 5250) 32K,2-way 32K,2-way,4-cycles 1M,16-way,21-cycles
A57 48K,3-way 32K,2-way,5-cycles(?) 512K-2M,16-way,??-cycles
Denver 128K,4-way 64K,4-way,?-cycles 2M,16-way,18-cycles
A8 64K,?-way 64K,?-way,4-cycles 1M,??-way,??-cycles + 4M L3
Silvermont 32K,8-way 24K,6-way,3-cycles 1M,16-way,14-cycles

I include the A15 only to see the L2 latency at 1MB. A57 may be a little better, but I'm not sure. Anybody has the numbers?

So of the modern 64-bit mobile CPUs, I would say A57 has the worst cache hierarchy. Unless the L2 is faster than Silvermont's at 1MB (because its L1 is significantly worse). But I doubt it is, I would say the L2 is closer to 20 cycles than to 10.
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TopicPosted ByDate
ARM announces A72Maynard Handley2015/02/03 12:36 PM
  ARM announces A72anon2015/02/03 01:53 PM
    ARM announces A72Hugo DĂ©charnes2015/02/03 02:20 PM
      ARM announces A72juanrga2015/02/03 05:15 PM
        ARM announces A72Wilco2015/02/04 01:58 AM
          ARM announces A72Eric Bron2015/02/04 02:48 AM
            ARM announces A72none2015/02/04 03:24 AM
              ARM announces A72Eric Bron2015/02/04 03:42 AM
                ARM announces A72Exophase2015/02/04 08:01 AM
                  ARM announces A72Anon2015/02/04 08:35 AM
                    ARM announces A72Exophase2015/02/04 08:58 AM
                      ARM announces A72Groo2015/02/04 10:24 AM
                ARM Marketing, BS up to my earsDavid Kanter2015/02/04 11:51 AM
                  ARM Marketing, BS up to my earsMaynard Handley2015/02/04 02:59 PM
                    ARM Marketing, BS up to my earsDavid Kanter2015/02/04 03:21 PM
                  ARM Marketing, BS up to my earsGroo2015/02/04 03:30 PM
          ARM announces A72juanrga2015/02/04 05:23 AM
            ARM announces A72Wilco2015/02/04 04:01 PM
              ARM announces A72juanrga2015/02/04 05:06 PM
        ARM announces A72Anon2015/02/04 02:28 AM
          ARM announces A72juanrga2015/02/04 05:31 AM
            ARM announces A72Aaron Spink2015/02/04 07:49 AM
      ARM announces A72Ronald Maas2015/02/03 08:23 PM
        ARM announces A72Seni2015/02/04 01:19 AM
          ARM announces A72Maynard Handley2015/02/04 11:42 AM
            ARM announces A72Seni2015/02/04 01:33 PM
              ARM announces A72dmcq2015/02/04 01:57 PM
            ARM announces A72Ronald Maas2015/02/04 07:42 PM
        ARM announces A72anon2015/02/04 06:19 AM
          ARM announces A72Exophase2015/02/04 08:31 AM
            ARM announces A72David Kanter2015/02/04 11:25 AM
              ARM announces A72Exophase2015/02/04 02:33 PM
                ARM announces A72anon2015/02/04 11:27 PM
                  ARM announces A72 (fixed format)anon2015/02/04 11:29 PM
                  ARM announces A72Exophase2015/02/05 12:11 AM
                    ARM announces A72anon2015/02/05 01:02 AM
            ARM announces A72anon2015/02/04 06:57 PM
  ARM announces A72Wilco2015/02/03 02:39 PM
    ARM announces A72Maynard Handley2015/02/03 03:13 PM
      ARM announces A72anon2015/02/03 03:29 PM
      ARM announces A72Wilco2015/02/03 03:44 PM
    ARM announces A72David Kanter2015/02/04 10:56 AM
      ARM announces A72Peter Greenhalgh2015/02/04 11:56 AM
        ARM announces A72Aaron Spink2015/02/04 12:59 PM
          ARM announces A72Alberto2015/02/07 11:22 AM
            ARM announces A72Exophase2015/02/07 11:47 AM
              ARM announces A72Alberto2015/02/07 01:44 PM
                ARM announces A72Exophase2015/02/07 03:35 PM
                  ARM announces A72Alberto2015/02/08 02:09 AM
                    ARM announces A72Exophase2015/02/08 12:05 PM
              ARM announces A72David Kanter2015/02/08 01:39 AM
                ARM announces A72dmcq2015/02/08 05:14 AM
                  ARM announces A72Michael S2015/02/08 05:38 AM
                    ARM announces A72Gabriele Svelto2015/02/10 06:11 AM
                      ARM announces A72Jouni Osmala2015/02/10 12:24 PM
                        slit vs unifiedMichael S2015/02/10 02:57 PM
                          slit vs unifieddmcq2015/02/11 06:44 AM
                  ARM announces A72Doug S2015/02/08 10:00 AM
                ARM announces A72Exophase2015/02/08 11:57 AM
        ARM announces A72dmcq2015/02/04 02:10 PM
        ARM announces A72David Kanter2015/02/04 03:28 PM
      ARM announces A72Wilco2015/02/04 02:59 PM
        ARM announces A72Aaron Spink2015/02/04 10:31 PM
        Intel 32nm vs 14 nmMichael S2015/02/05 02:03 AM
          Intel 32nm vs 14 nmWilco2015/02/05 03:27 AM
            Intel 32nm vs 14 nmDavid Kanter2015/02/05 10:05 AM
              Intel 32nm vs 14 nmcarop2015/02/05 12:12 PM
                Normalize to drawn or effective width?David Kanter2015/02/05 12:45 PM
                  Normalize to drawn or effective width?carop2015/02/05 03:40 PM
                    Normalize to drawn or effective width?David Kanter2015/02/06 01:44 PM
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