Normalize to drawn or effective width?

By: David Kanter (dkanter.delete@this.realworldtech.com), February 5, 2015 12:45 pm
Room: Moderated Discussions
carop (carop.delete@this.somewhere.org) on February 5, 2015 12:12 pm wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on February 5, 2015 10:05 am wrote:
> >
> > In terms of density, TSMC is about half-way between Intel's 14nm
> > and 22nm. But in terms of performance it is equivalent to 22nm.
> >
>
> When you claim performance parity between Intel N22 and TSMC N16 are you
> bearing in mind that Intel normalize the current per device footprint?

Yes, I am. I've heard a number of people make the argument that it's better to normalize to Weff, but the reasoning doesn't make sense to me (why not calculate leakage normalized to Weff?). Moreover, most other companies are not disclosing effective width, so it makes things even harder.

The way I see it, layout width is the constraint for designers, and it is also the way to measure conventional planar devices.

I can see how Ion/Weff might be useful in some cases, but I haven't heard good arguments why it is a better metric than Ion/width.

> Once the current is normalized per actual device width, the numbers
> are 20~30% smaller than those Intel show in their papers.
>
> IEDM 2014 Comparison

I don't find this argument particularly compelling, in part because I heard it mostly from companies that aren't disclosing much about their own FinFET process (e.g., TSMC).

David
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                Normalize to drawn or effective width?David Kanter2015/02/05 12:45 PM
                  Normalize to drawn or effective width?carop2015/02/05 03:40 PM
                    Normalize to drawn or effective width?David Kanter2015/02/06 01:44 PM
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