carop (carop.delete@this.somewhere.org) on February 5, 2015 3:40 pm wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on February 5, 2015 12:45 pm wrote:
> >
> > Yes, I am. I've heard a number of people make the argument that it's better to normalize to Weff,
> > but the reasoning doesn't make sense to me (why not calculate leakage normalized to Weff?).
> > Moreover, most other companies are not disclosing effective width, so it makes things even harder.
> >
>
> With the gate wrapping around the fin, you effectively get higher device width per footprint of the device and
> for a given device footprint (which is typically set by number of metal tracks you allocate to a given standard
> cell and how much space is wasted to isolate devices and plug gate contacts) you get higher drive current.

Yes, we are totally agreed here.

>The
> catch is that the higher Ion comes at the price of higher capacitance which Intel is not quoting.

Well yes, that's how you get better control over the transistor.

> > I don't find this argument particularly compelling, in part because I heard it mostly from
> > companies that aren't disclosing much about their own FinFET process (e.g., TSMC).
> >
>
> I believe it was IBM that suggested active current (Ieff) as a metric of speed in an IEDM paper.

Ieffective is something else. Ieffective is a metric that Intel had quoted numerous times. I cannot quite recall the definition, but I think its

Ieffective = Average of Ion @ Vgs=Vdd and Ion @ Vgs = 1/2 Vdd

It's essentially a measure of how well the transitor performs when not fully on, but in the upper end of the linear region.

> The figure is from the STM FD-SOI N10 paper which was presented at IEDM 2014.
>
> - [13] is Intel@VLSI2012
> - [14] is Intel@IEDM2012
> - [15] is TSMC@IEDM2013
>
> I included the figure for a quick Intel N22 and TSMC N16 device comparison. No, IBM did not normalize
> drive current to footprint in their IEDM 2014 SOI FinFET paper either. Intel seems to be the
> only manufacturer normalizing the drive current of their FinFET devices to footprint. I do not
> want to argue with that, but this is something to bear in mind when benchmarking.

I know that normalizing to effective width is a valid metric, but my point is that I don't understand exactly what it is saying. I know what normalizing to drawn width means.

> At N22, Intel used a fin height of about 35nm and fin pitch of 60nm. At N14, they increased fin height to
> 42nm and dropped fin pitch to 42nm. So the shrink from N22 to N14 increased channel width by 70% but drive
> current by less than 30% (15% nMOS, 41% pMOS). How do you explain this performance difference then?

Well it could be due to stress or other factors that determine performance.

David