ARM published the Cortex-A72 Technical Reference Manual. Somewhat surprisingly both cores use the exact same high-level architecture: 3-wide instruction decoder, 8 pipelines and same L1+ L2 cache configuration.

Only differences I could find between A72 and A57:
1) Supports 4 MB L2 cache size (configurable)
2) Automatic hardware prefetcher that generates prefetches targeting the L1D cache and the L2 cache

Ronald