Ronald Maas (rmaas.delete@this.wiwo.nl) on March 5, 2015 8:01 am wrote:
> ARM published the Cortex-A72 Technical Reference Manual. Somewhat surprisingly both cores use the exact same
> high-level architecture: 3-wide instruction decoder, 8 pipelines and same L1+ L2 cache configuration.
>
> Only differences I could find between A72 and A57:
> 1) Supports 4 MB L2 cache size (configurable)
> 2) Automatic hardware prefetcher that generates prefetches targeting the L1D cache and the L2 cache


I've found some interesting tidbits mentioning FPU improvements on LinkedIn:
David Lutz profile

I quote:

Cortex-A72 (Maia): I completely redesigned the FPU, making major improvements in latency and energy, and I completed the project in only 9 months. The new unit can do a left-to-right in-order sum of 4 products (using FMAs) in only 13 cycles, and is about 30% faster than Cortex-A57 on SpecFP (constant clock). More than half of this speedup is due to FP datapath improvements.

and some boasting:

My FPUs are influenced by my many years as a programmer. Some of the most compute intensive parts of programs (particularly sums of products) execute with exceptional speed on my designs, taking only 1/2 to 2/3 of the cycles required by an IBM or Intel implementation. In fact I believe my Cortex-A72 design has the fastest datapath of any IEEE 754-2008 compliant FPU, and my next design is going to be both smaller and faster.