juanrga (nospam.delete@this.juanrga.com) on March 7, 2015 7:06 pm wrote:
> Brett (ggtgp.delete@this.yahoo.com) on March 7, 2015 2:56 pm wrote:
> > juanrga (nospam.delete@this.juanrga.com) on March 6, 2015 6:22 pm wrote:
> > > I don't expect K12 to be significantly better than Vulcan.
> >
> > Is that per thread? Vulcan is 4 way threaded. Per die size, MIPS/watt?
>
> Performance per core.
>
> > Vulcan slides show 8 fetch, 4 issue, 60 entry scheduler, 6 ports, unknown completion.
>
> Vulcan is 6-issue.

Intel Haswell is limited to 4 decode, and I misread the Vulcan specs, my concerns were misplaced.

> > High end chips tend to be 6 decode, 6 issue, 192 entry scheduler, ~8 ports, 6 completion.
>
> 192 is the size of the ROB on Haswell. Vulcan has a 180 entries ROB.
>
> > The 4 issue sticks out like a sore thumb, I hope there is some opcode merging going on. I also hope
> > that scheduler is not shared four ways, it is to small to be competitive as is. The previous MIPS chip
> > with similar specs was tiny, you can put lots of them on a die, and win benchmarks that way.
>
> The target is 2x more performance than the MIPS core and 90% of Haswell IPC.

Looking impressive, I assume this is a server/network class chip, will Vulcan not bother with the obsolete overhead of ARM32 mode?

> > On the good side it does have three load/store ports, supporting 2 loads or 3
> > stores, which sounds backwards to me, most code has more loads than stores.
> > https://hpcuserforum.com/presentations/santafe2014/Broadcom%20Monday%20night.pdf
> >
> > I am really expecting K12 to be wider than Bulldozer.
>
> I also.