By: Michael S (already5chosen.delete@this.yahoo.com), March 8, 2015 1:30 am
Room: Moderated Discussions
Brett (ggtgp.delete@this.yahoo.com) on March 7, 2015 9:10 pm wrote:
> Anon (no.delete@this.email.com) on March 7, 2015 6:43 pm wrote:
> > anon (example.delete@this.example.com) on March 7, 2015 5:01 pm wrote:
> > > Brett (ggtgp.delete@this.yahoo.com) on March 7, 2015 2:56 pm wrote:
> > > > juanrga (nospam.delete@this.juanrga.com) on March 6, 2015 6:22 pm wrote:
> > > > > I don't expect K12 to be significantly better than Vulcan.
> > > >
> > > > Is that per thread? Vulcan is 4 way threaded. Per die size, MIPS/watt?
> > > > Vulcan slides show 8 fetch, 4 issue, 60 entry scheduler, 6 ports, unknown completion.
> > > >
> > > > High end chips tend to be 6 decode, 6 issue, 192 entry scheduler, ~8 ports, 6 completion.
> > > >
> > >
> > > Other than Cyclone, which cores fit this description?
> >
> > Ah, you have probably forgotten that in Bretts world, Cyclone
> > is both A highend chip, and THE ONLY high end chip..
> > Anyone else who doesnt follow that formula exactly, is by definition
> > not 'a high end chip' (regardless of their performance).
>
> That description is also a good match for Intel Haswell, the other benchmark to beat. ;););)
>
Except that Haswell decode is 4-way, in-order issue (=renamer) is also 4-way as is a completions (=retirement). OoO dispatch is indeed 8-way, but advantage it gives over 6-way dispatch of Ivy Bridge is miniscule, except, may be, few classes of SIMD kernels.
As to number of scheduler entries, I am not sure what it means. Haswell has 60 reservation stations (Intel prefers to say, 60-entry reservation station) and can handle 192 uops in flight. Which of the two numbers considered "scheduler entries" ?
. manual talks about 192 uops in flight, but I don't think that you can call it 192 schedulers.
> Juanrga gave a good reply, my concerns are settled, Vulcan looks to do well.
>
Details matter. Sometimes they matter more than width and number of entries in various structures. And they (details) are mostly unknown.
> Anon (no.delete@this.email.com) on March 7, 2015 6:43 pm wrote:
> > anon (example.delete@this.example.com) on March 7, 2015 5:01 pm wrote:
> > > Brett (ggtgp.delete@this.yahoo.com) on March 7, 2015 2:56 pm wrote:
> > > > juanrga (nospam.delete@this.juanrga.com) on March 6, 2015 6:22 pm wrote:
> > > > > I don't expect K12 to be significantly better than Vulcan.
> > > >
> > > > Is that per thread? Vulcan is 4 way threaded. Per die size, MIPS/watt?
> > > > Vulcan slides show 8 fetch, 4 issue, 60 entry scheduler, 6 ports, unknown completion.
> > > >
> > > > High end chips tend to be 6 decode, 6 issue, 192 entry scheduler, ~8 ports, 6 completion.
> > > >
> > >
> > > Other than Cyclone, which cores fit this description?
> >
> > Ah, you have probably forgotten that in Bretts world, Cyclone
> > is both A highend chip, and THE ONLY high end chip..
> > Anyone else who doesnt follow that formula exactly, is by definition
> > not 'a high end chip' (regardless of their performance).
>
> That description is also a good match for Intel Haswell, the other benchmark to beat. ;););)
>
Except that Haswell decode is 4-way, in-order issue (=renamer) is also 4-way as is a completions (=retirement). OoO dispatch is indeed 8-way, but advantage it gives over 6-way dispatch of Ivy Bridge is miniscule, except, may be, few classes of SIMD kernels.
As to number of scheduler entries, I am not sure what it means. Haswell has 60 reservation stations (Intel prefers to say, 60-entry reservation station) and can handle 192 uops in flight. Which of the two numbers considered "scheduler entries" ?
. manual talks about 192 uops in flight, but I don't think that you can call it 192 schedulers.
> Juanrga gave a good reply, my concerns are settled, Vulcan looks to do well.
>
Details matter. Sometimes they matter more than width and number of entries in various structures. And they (details) are mostly unknown.