Brett (ggtgp.delete@this.yahoo.com) on March 7, 2015 2:56 pm wrote:
> juanrga (nospam.delete@this.juanrga.com) on March 6, 2015 6:22 pm wrote:
> > I don't expect K12 to be significantly better than Vulcan.
>
> Is that per thread? Vulcan is 4 way threaded. Per die size, MIPS/watt?
> Vulcan slides show 8 fetch, 4 issue, 60 entry scheduler, 6 ports, unknown completion.
>
> High end chips tend to be 6 decode, 6 issue, 192 entry scheduler, ~8 ports, 6 completion.
>
> The 4 issue sticks out like a sore thumb, I hope there is some opcode merging going on. I also hope
> that scheduler is not shared four ways, it is to small to be competitive as is. The previous MIPS chip
> with similar specs was tiny, you can put lots of them on a die, and win benchmarks that way.
>
> On the good side it does have three load/store ports, supporting 2 loads or 3
> stores, which sounds backwards to me, most code has more loads than stores.
> https://hpcuserforum.com/presentations/santafe2014/Broadcom%20Monday%20night.pdf
>
> I am really expecting K12 to be wider than Bulldozer.

On paper, Vulcan sounds good. But too many details are missing:

1. Branch prediction details
2. Prefetching
3. Load/store buffering strategy

Not to mention system level issues. Are they claiming they will beat a Haswell Xeon E3? I could believe that. I am much more skeptical they can beat a Haswell EP or EX.

I'd also point out that anything on TSMC 16nm won't compete with Haswell, but instead with Broadwell.

David