Brett (ggtgp.delete@this.yahoo.com) on March 30, 2015 6:50 pm wrote:
> juanrga (nospam.delete@this.juanrga.com) on March 8, 2015 6:48 am wrote:
> > Brett (ggtgp.delete@this.yahoo.com) on March 7, 2015 9:26 pm wrote:
> > > juanrga (nospam.delete@this.juanrga.com) on March 7, 2015 7:06 pm wrote:
> > > > Brett (ggtgp.delete@this.yahoo.com) on March 7, 2015 2:56 pm wrote:
> > > > > juanrga (nospam.delete@this.juanrga.com) on March 6, 2015 6:22 pm wrote:
> > > > > > I don't expect K12 to be significantly better than Vulcan.
> > > > >
> > > > > Is that per thread? Vulcan is 4 way threaded. Per die size, MIPS/watt?
> > > >
> > > > Performance per core.
> > > >
> > > > > Vulcan slides show 8 fetch, 4 issue, 60 entry scheduler, 6 ports, unknown completion.
> > > >
> > > > Vulcan is 6-issue.
> > >
> > > Looking impressive, I assume this is a server/network class chip,
> > > will Vulcan not bother with the obsolete overhead of ARM32 mode?
> >
> > The decoder implements the full A64 mode but only the user
> > mode of A32. This combination supports 32-bit ARM
> > applications running on a 64-bit operating system, but it does not allow for 32-bit operating systems.
> >
> > I had preferred only A64 support because I don't think it needs to support
> > legacy 32bit apps, but... Maybe Vulcan II eliminates all legacy.
>
> Does the Vulcan do opcode merging for reads to the same cache line?
> Are the instructions that read two values for two registers cracked, or used as is?

I think we'll have to wait a bit to see exactly what they do! and perhaps even then that sort of stuff won't be explicitly given out any more than Apple has said exactly how their chips work.

Personally though looking at the outline diagrams they've put out, if those are anyway accurate I can't see how they can get the performance they talk about with the number of execution units they have without trying to merge operations and avoiding any cracking.