By: David Kanter (dkanter.delete@this.realworldtech.com), April 21, 2015 2:53 pm
Room: Moderated Discussions
Here comes my latest article, complete with predictions for future process technology at Intel.
On the eve of the 50th anniversary of Moore’s Law, the future of silicon CMOS is an open question. With rising costs and uncertain benefits, some semiconductor companies have questioned the wisdom of pursuing further scaling. I predict that Intel's 10nm process technology will use Quantum Well FETs (QWFETs) with a 3D fin geometry, InGaAs for the NFET channel, and strained Germanium for the PFET channel, enabling lower voltage and more energy efficient transistors in 2016, and the rest of the industry will follow suit at the 7nm node.
The full article is available at http://www.realworldtech.com/intel-10nm-qwfet/
As always, post questions, comments, feedback, flames, etc. here.
David
On the eve of the 50th anniversary of Moore’s Law, the future of silicon CMOS is an open question. With rising costs and uncertain benefits, some semiconductor companies have questioned the wisdom of pursuing further scaling. I predict that Intel's 10nm process technology will use Quantum Well FETs (QWFETs) with a 3D fin geometry, InGaAs for the NFET channel, and strained Germanium for the PFET channel, enabling lower voltage and more energy efficient transistors in 2016, and the rest of the industry will follow suit at the 7nm node.
The full article is available at http://www.realworldtech.com/intel-10nm-qwfet/
As always, post questions, comments, feedback, flames, etc. here.
David
