David Kanter (dkanter.delete@this.realworldtech.com) on April 21, 2015 2:53 pm wrote:
> Here comes my latest article, complete with predictions for future process technology at Intel.
>
> On the eve of the 50th anniversary of Moore’s Law, the future of silicon CMOS is an open question. With rising
> costs and uncertain benefits, some semiconductor companies have questioned the wisdom of pursuing further scaling.
> I predict that Intel's 10nm process technology will use Quantum Well FETs (QWFETs) with a 3D fin geometry, InGaAs
> for the NFET channel, and strained Germanium for the PFET channel, enabling lower voltage and more energy efficient
> transistors in 2016, and the rest of the industry will follow suit at the 7nm node.
>
> The full article is available at http://www.realworldtech.com/intel-10nm-qwfet/
>
> As always, post questions, comments, feedback, flames, etc. here.
>
> David

You're discussing three (apparently) orthogonal ideas: QWFETs, III-V (or Germanium) transistors, and 10nm. Are there good reasons to believe these HAVE to be yoked together? Is it possible, for example (especially given Intel's difficulties and delays at 14nm) that they produce Skylake on 14nm, then Cannonlake on 14nm with QWFET and III-V? This would be something of a departure from the standard tick-tock model, but that model is merely a guideline.
Doing this would allow them to maintain the microarchitecture cadence rather than being forced to slow down to match process upgrades, would allow them to debug QWFET issues on a somewhat better known process, and would give them another 18 months or so to deal with 10nm issues.