The classic argument for using compound semiconductors is their much higher carrier mobility than pure Silicon. Meaning electrons and holes will move faster through a transistor channel at a given voltage. The relation to 10nm is that one needs to decrease voltage as geometries shrink and III-V compounds will offset transistor performance degradation by doing so. There's other stuff going on with this transistor, like the use of high-k insulators that also improve scaling, but I haven't had time to study to papers to understand the motivation for the complex substrate layers (as shown in the 2009 IEDM paper).

Maynard Handley (name99.delete@this.name99.org) on April 21, 2015 8:57 pm wrote:
>
> You're discussing three (apparently) orthogonal ideas: QWFETs, III-V (or Germanium) transistors,
> and 10nm. Are there good reasons to believe these HAVE to be yoked together? Is it possible,
> for example (especially given Intel's difficulties and delays at 14nm) that they produce Skylake
> on 14nm, then Cannonlake on 14nm with QWFET and III-V? This would be something of a departure
> from the standard tick-tock model, but that model is merely a guideline.
> Doing this would allow them to maintain the microarchitecture cadence rather than being forced
> to slow down to match process upgrades, would allow them to debug QWFET issues on a somewhat better
> known process, and would give them another 18 months or so to deal with 10nm issues.
>