By: Otis (otistd.delete@this.gmail.com), April 22, 2015 7:48 am
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on April 21, 2015 2:53 pm wrote:
> Here comes my latest article, complete with predictions for future process technology at Intel.
>
> On the eve of the 50th anniversary of Moore’s Law, the future of silicon CMOS is an open question. With rising
> costs and uncertain benefits, some semiconductor companies have questioned the wisdom of pursuing further scaling.
> I predict that Intel's 10nm process technology will use Quantum Well FETs (QWFETs) with a 3D fin geometry, InGaAs
> for the NFET channel, and strained Germanium for the PFET channel, enabling lower voltage and more energy efficient
> transistors in 2016, and the rest of the industry will follow suit at the 7nm node.
>
> The full article is available at http://www.realworldtech.com/intel-10nm-qwfet/
>
> As always, post questions, comments, feedback, flames, etc. here.
>
> David
That is interesting speculation- but I fear your predictions are way too aggressive. The infrastructure for running III-V on 300mm Si in HVM isn't there yet. From and EHS perspective alone, InGaAs or GaAs is a significant headache, not because of As toxicity as you might think, but because of As carcinogenicity- meaning zero exposure is the goal. The first III-V on 300mm Si was run in Albany withing the past 2 years and reported. That takes significant effort even in a research Fab, converting an HVM fab to run it regularly will be difficult. For every step with exposed GaAs/InGaAs surface you need to have a tool that is certified to run III-V, and very few of them are. Increased maintenance cost for handing As contaminated parts, etc. is another problem. Frankly it's just not there. Last year UCSB reported the first III-V devices that are competitive with 22nm Si, but those are planar and will need some development to build into a scaled/scalable fin structure. Finally, the distinction between QWFETs and FinFETs is not so clear as you make it seem- Intels III-V Tri-Gates which you show, do not have a large band gap barrier isolating the channel surface, as in a traditiona QW, so they are really just TriGate- or TriGate is essentially a QW, depending on how you want to look at it- it's a bit fuzzy.
Regarding Ge, there are signicant integration issues with pure Ge, and even high Ge SiGe channels that you seem unaware of or at least don't mention. However, Ge is in the fab already (SiGe Souce/Drain) and can be handled easily without the additional infrastructure and re-tooling needed for III-V. Actually the IBM alliance partners have low Ge SiGe channels running in HVM. In any case low Ge SiGe (<50% probably around 20-30% Ge) could show up at Intel for 10/7nm. Here is a reasonable set of predictions to counter yours.
-Intel will introduce low Ge SiGe channels for PFET only at 10nm or possibly 7nm.
-Intel will introduce a Gate All Around (GAA) stacked nanowire FET structure at 7nm or possibly 5nm
-Intel will not use III-V for logic device channels prior to 5nm except possibly as a peripheral device integrated for mobile apps in the MOL or BEOL (not at the transistor level)- personally I seriously doubt III-V will come to logic at all, but certainly not before 5nm.
> Here comes my latest article, complete with predictions for future process technology at Intel.
>
> On the eve of the 50th anniversary of Moore’s Law, the future of silicon CMOS is an open question. With rising
> costs and uncertain benefits, some semiconductor companies have questioned the wisdom of pursuing further scaling.
> I predict that Intel's 10nm process technology will use Quantum Well FETs (QWFETs) with a 3D fin geometry, InGaAs
> for the NFET channel, and strained Germanium for the PFET channel, enabling lower voltage and more energy efficient
> transistors in 2016, and the rest of the industry will follow suit at the 7nm node.
>
> The full article is available at http://www.realworldtech.com/intel-10nm-qwfet/
>
> As always, post questions, comments, feedback, flames, etc. here.
>
> David
That is interesting speculation- but I fear your predictions are way too aggressive. The infrastructure for running III-V on 300mm Si in HVM isn't there yet. From and EHS perspective alone, InGaAs or GaAs is a significant headache, not because of As toxicity as you might think, but because of As carcinogenicity- meaning zero exposure is the goal. The first III-V on 300mm Si was run in Albany withing the past 2 years and reported. That takes significant effort even in a research Fab, converting an HVM fab to run it regularly will be difficult. For every step with exposed GaAs/InGaAs surface you need to have a tool that is certified to run III-V, and very few of them are. Increased maintenance cost for handing As contaminated parts, etc. is another problem. Frankly it's just not there. Last year UCSB reported the first III-V devices that are competitive with 22nm Si, but those are planar and will need some development to build into a scaled/scalable fin structure. Finally, the distinction between QWFETs and FinFETs is not so clear as you make it seem- Intels III-V Tri-Gates which you show, do not have a large band gap barrier isolating the channel surface, as in a traditiona QW, so they are really just TriGate- or TriGate is essentially a QW, depending on how you want to look at it- it's a bit fuzzy.
Regarding Ge, there are signicant integration issues with pure Ge, and even high Ge SiGe channels that you seem unaware of or at least don't mention. However, Ge is in the fab already (SiGe Souce/Drain) and can be handled easily without the additional infrastructure and re-tooling needed for III-V. Actually the IBM alliance partners have low Ge SiGe channels running in HVM. In any case low Ge SiGe (<50% probably around 20-30% Ge) could show up at Intel for 10/7nm. Here is a reasonable set of predictions to counter yours.
-Intel will introduce low Ge SiGe channels for PFET only at 10nm or possibly 7nm.
-Intel will introduce a Gate All Around (GAA) stacked nanowire FET structure at 7nm or possibly 5nm
-Intel will not use III-V for logic device channels prior to 5nm except possibly as a peripheral device integrated for mobile apps in the MOL or BEOL (not at the transistor level)- personally I seriously doubt III-V will come to logic at all, but certainly not before 5nm.
