RWT Article: What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETs

Article: What's Next for Moore's Law? For Intel, III+V = 10nm QWFETs
By: David Ball (dball.delete@this.booksnbytes.com), April 22, 2015 11:55 am
Room: Moderated Discussions
Exophase (exophase.delete@this.gmail.com) on April 21, 2015 9:25 pm wrote:
> Maynard Handley (name99.delete@this.name99.org) on April 21, 2015 8:57 pm wrote:
> > You're discussing three (apparently) orthogonal ideas: QWFETs, III-V (or Germanium) transistors,
> > and 10nm. Are there good reasons to believe these HAVE to be yoked together? Is it possible,
> > for example (especially given Intel's difficulties and delays at 14nm) that they produce Skylake
> > on 14nm, then Cannonlake on 14nm with QWFET and III-V? This would be something of a departure
> > from the standard tick-tock model, but that model is merely a guideline.
> > Doing this would allow them to maintain the microarchitecture cadence rather than being forced
> > to slow down to match process upgrades, would allow them to debug QWFET issues on a somewhat better
> > known process, and would give them another 18 months or so to deal with 10nm issues.
> >
>
> A big motivator for Moore's Law has been lowering cost per transistor. Outside of being an easier
> design target for straightening out the new process, the financial allure of the tick is allowing
> them to sell (what's close to) the previous design at a lower cost. Lower power consumption or higher
> performance are fringe benefits in comparison. At least for the big cores where Intel has a lock
> the markets they're playing in (even the tablets are something of a class unto themselves)
>
> Maybe such a thing would be appealing for Atom but I'm skeptical it'd be something they'd do
> for Cannonlake, something that'd make it (possibly significantly) more expensive than Skylake.

I look forward to reading the article. This discussion makes me think of some articles I've read recently on SemiWiki

Intel Inline with reduced expectations-2015 flat to down-Slashing Capex talks about reduced capex delaying 10 nm and later nodes. It also speculates about whether TSMC might catch Intel.

Moore’s Law is dead, long live Moore’s Law - link is to part one - there are five parts currently. Part 4 of the article talks about the problems for logic with smaller nodes and how they might be dealt with.

David Ball
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TopicPosted ByDate
RWT Article: What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETsDavid Kanter2015/04/21 02:53 PM
  RWT Article: What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETsExophase2015/04/21 03:42 PM
  RWT Article: What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETsJoe2015/04/21 06:06 PM
  RWT Article: What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETsMaynard Handley2015/04/21 08:57 PM
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                      Comparison of 14nm Broadwell and 22nm HaswellAlberto2015/07/17 01:22 PM
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