By: David Kanter (dkanter.delete@this.realworldtech.com), April 23, 2015 12:28 pm
Room: Moderated Discussions
Paul (paclifton.delete@this.gmail.com) on April 22, 2015 5:20 pm wrote:
> I'm pretty much aligned with Otis' views but feel he could be a bit more adamant on some points.
>
> FinFETs, with a fin width less than 10 nm are already quantum well FETs (QWFETs), and
> entered Intel HVM at 22 nm node. Sorry David Kanter, your predictions 4 and 6 predicting
> the advent of QWFETs at 10 nm (Intel) and 7 nm (the rest) are already fails.
Hrmm, I'm not so worried about those predictions.
> Talk of high mobility materials should be discouraged in the nanometer era. Electron transport is now largely
> ballistic and the old mobility concept is barely relevant any longer. Longitudinal and transverse effective
> masses and band degeneracies are more important considerations now and going forward. Sure, mobility and effective
> mass are linked but we need to get away from the old concepts. Even then more prosaic factors such as contact
> resistance / Rsd might well be the over-riding considerations regarding transistor performance.
I'm not a device physicist, but I certainly agree that resistance is a really big problem for highly scaled devices.
> David Kanter's statement "classic CMOS behaves poorly at supply voltages below 1V, due to the bandgap
> structure of silicon" is hard to parse: "bandgap structure" itself is an ambiguous term not used by
> device physicists - band gap or band structure?
That was a typo, I meant band gap; thanks for pointing it out, I fixed it.
Reducing operating voltage has everything to do with
> optimizing the transistor's subthreshold characteristic and its variability and has almost nothing
> to do with band gap or band structure.
There was a paper at VLSI 2012 that demonstrated at fixed 100nA/um Ioff, that planar InGaAs is about 50% better than silicon at 0.5V Vcc. That is with III-V QWFETs that have 1.6X higher Rext.
They also had simulated results that looked even better, but those required QWFETs with comparable Rext and EOT as the silicon (which might be optimistic).
The paper is III-V Field Effect Transistors for Future Ultra-Low Power Applications by G. Dewey, et al. if you want to look it up.
>I don't think there's an argument that semiconductors other
> than silicon can improve the ability of digital circuits to function at lower voltages, unless one
> invokes tunneling source ideas (not mentioned in the article under discussion here).
I think TFETs are much further out...but I'm not sure I'd agree with you. Intel certainly seems to be making arguments otherwise. Although they'd agree that TFETs are quite impressive, I have no idea if they can even be fabricated in volume.
>Maybe he means
> that if low voltage operation could be achieved by superior control of the sub-threshold behavior,
> then a different material could perform better at low voltages? That's a lot of coulds...
My guess is that they will aim for similar sub-threshold control. I don't think III-Vs are good for low leakage, only for high performance devices.
> To repeat Otis "Last year UCSB reported the first III-V devices that are competitive with 22nm Si". That's
> far from compelling! Anyone seen data showing any nanometer scale III-V
> to strained silicon to make the additional huge effort to bring III-Vs to manufacturing worthwhile? RF performance
> metrics (fT, fmax, gm) don't count in digital CMOS which is dominated by interconnect RC.
I don't believe Intel has made all their data public. Especially not if they plan to actually do anything with it.
> The balance of probabilities (~90%) points to silicon channels continuing at least up to the 10 nm node.
> Since germanium offers potential improvements for both n-type and p-type, that is perhaps the only realistic
> contender beyond 10 nm. Co-integration of Ge and III-V materials? Likely not ever (<10%).
Alright! Glad to see a counter-prediction. I agree that Ge seems easier, especially since you can get away with SiGe channels instead of pure Ge (as a first step).
David
> I'm pretty much aligned with Otis' views but feel he could be a bit more adamant on some points.
>
> FinFETs, with a fin width less than 10 nm are already quantum well FETs (QWFETs), and
> entered Intel HVM at 22 nm node. Sorry David Kanter, your predictions 4 and 6 predicting
> the advent of QWFETs at 10 nm (Intel) and 7 nm (the rest) are already fails.
Hrmm, I'm not so worried about those predictions.
> Talk of high mobility materials should be discouraged in the nanometer era. Electron transport is now largely
> ballistic and the old mobility concept is barely relevant any longer. Longitudinal and transverse effective
> masses and band degeneracies are more important considerations now and going forward. Sure, mobility and effective
> mass are linked but we need to get away from the old concepts. Even then more prosaic factors such as contact
> resistance / Rsd might well be the over-riding considerations regarding transistor performance.
I'm not a device physicist, but I certainly agree that resistance is a really big problem for highly scaled devices.
> David Kanter's statement "classic CMOS behaves poorly at supply voltages below 1V, due to the bandgap
> structure of silicon" is hard to parse: "bandgap structure" itself is an ambiguous term not used by
> device physicists - band gap or band structure?
That was a typo, I meant band gap; thanks for pointing it out, I fixed it.
Reducing operating voltage has everything to do with
> optimizing the transistor's subthreshold characteristic and its variability and has almost nothing
> to do with band gap or band structure.
There was a paper at VLSI 2012 that demonstrated at fixed 100nA/um Ioff, that planar InGaAs is about 50% better than silicon at 0.5V Vcc. That is with III-V QWFETs that have 1.6X higher Rext.
They also had simulated results that looked even better, but those required QWFETs with comparable Rext and EOT as the silicon (which might be optimistic).
The paper is III-V Field Effect Transistors for Future Ultra-Low Power Applications by G. Dewey, et al. if you want to look it up.
>I don't think there's an argument that semiconductors other
> than silicon can improve the ability of digital circuits to function at lower voltages, unless one
> invokes tunneling source ideas (not mentioned in the article under discussion here).
I think TFETs are much further out...but I'm not sure I'd agree with you. Intel certainly seems to be making arguments otherwise. Although they'd agree that TFETs are quite impressive, I have no idea if they can even be fabricated in volume.
>Maybe he means
> that if low voltage operation could be achieved by superior control of the sub-threshold behavior,
> then a different material could perform better at low voltages? That's a lot of coulds...
My guess is that they will aim for similar sub-threshold control. I don't think III-Vs are good for low leakage, only for high performance devices.
> To repeat Otis "Last year UCSB reported the first III-V devices that are competitive with 22nm Si". That's
> far from compelling! Anyone seen data showing any nanometer scale III-V
- logic
> to strained silicon to make the additional huge effort to bring III-Vs to manufacturing worthwhile? RF performance
> metrics (fT, fmax, gm) don't count in digital CMOS which is dominated by interconnect RC.
I don't believe Intel has made all their data public. Especially not if they plan to actually do anything with it.
> The balance of probabilities (~90%) points to silicon channels continuing at least up to the 10 nm node.
> Since germanium offers potential improvements for both n-type and p-type, that is perhaps the only realistic
> contender beyond 10 nm. Co-integration of Ge and III-V materials? Likely not ever (<10%).
Alright! Glad to see a counter-prediction. I agree that Ge seems easier, especially since you can get away with SiGe channels instead of pure Ge (as a first step).
David