III-V Tailored by Taylor?

Article: What's Next for Moore's Law? For Intel, III+V = 10nm QWFETs
By: David Kanter (dkanter.delete@this.realworldtech.com), April 23, 2015 2:35 pm
Room: Moderated Discussions
native gaas (undisclosed.delete@this.gmail.com) on April 22, 2015 4:27 am wrote:
> what's your take on Taylor's work with III-V?
>
> am curious about this dark horse.

I believe you are astroturfing, but I will indulge.

GaAs lost the digiital logic war to silicon for economic reasons. That fight is over.

1. Intel and TSMC will never pay for more expensive substrates AND pay to license an unproven technology, both companies are very cost sensitive.

Note that Taylor & Co. claim the cost is competitive with FD-SOI (which I doubt, but let's play nice). Nobody is using FD-SOI because of cost reasons. So the cost argument is silly.

2. It's not even remotely viable till 300mm wafers are available (and 450mm will be needed soon); being CMOS compatible doesn't mean a whole lot unless you are compatible with leading edge manufacturers like Intel, TSMC, GF, Samsung.

3. Silicon photonics are mostly likely to be done on a separate die and co-packaged, no point is adding to the cost of the silicon to add optical elements.

There's a reason why Intel's work all focuses around epitaxial growth of III-Vs and Ge on silicon, and it has to do with economics.

As it stands today, POET has made far less progress than SuVolta. The latter is working with Fujitsu and has some great results so far. And they aren't really making money yet.

Seems like a boutique and niche technology.

David
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