By: David Kanter (dkanter.delete@this.realworldtech.com), April 23, 2015 2:41 pm
Room: Moderated Discussions
carop (carop.delete@this.somewhere.org) on April 22, 2015 10:57 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on April 21, 2015 2:53 pm wrote:
> > Here comes my latest article, complete with predictions for future process technology at Intel.
> >
> > On the eve of the 50th anniversary of Moore’s Law, the future
> > of silicon CMOS is an open question. With rising
> > costs and uncertain benefits, some semiconductor companies
> > have questioned the wisdom of pursuing further scaling.
> > I predict that Intel's 10nm process technology will use Quantum
> > Well FETs (QWFETs) with a 3D fin geometry, InGaAs
> > for the NFET channel, and strained Germanium for the PFET channel,
> > enabling lower voltage and more energy efficient
> > transistors in 2016, and the rest of the industry will follow suit at the 7nm node.
> >
> > The full article is available at http://www.realworldtech.com/intel-10nm-qwfet/
> >
> > As always, post questions, comments, feedback, flames, etc. here.
> >
> > David
This is a great find - thanks!
> According to Victor Moroz @ Synopsys, there is no Group IV vs III-V combination champion. It
> is a close race with no clear winner, and the best choice depends on your chip specification.
> He thinks that Silicon is still the best channel material, at least for LP mobile devices.
I agree that silicon is best for low leakage (e.g., phones, tablets). He's totally spot on - Generally III-V/Ge doesn't improve leakage, but it's really great at ~0.5V.
> Moroz also concluded that nobody can pull off LP at 0.5V Vdd and that in order to
> have 0.5V Vdd the variability has to go down ~2x which he thinks is a stretch:
>
> http://www.avsusergroups.org/jtg_pdfs/2014_7moroz_Synopsis.pdf
Actually this is pretty consistent with what I've been saying. Silicon will be cointegrated with III-V/Ge, with the latter being used for high performance transistors and silicon for LP (or lower value stuff).
I suspect he might disagree with me on timing, but I think 7nm is within the realm of possibility.
David
> David Kanter (dkanter.delete@this.realworldtech.com) on April 21, 2015 2:53 pm wrote:
> > Here comes my latest article, complete with predictions for future process technology at Intel.
> >
> > On the eve of the 50th anniversary of Moore’s Law, the future
> > of silicon CMOS is an open question. With rising
> > costs and uncertain benefits, some semiconductor companies
> > have questioned the wisdom of pursuing further scaling.
> > I predict that Intel's 10nm process technology will use Quantum
> > Well FETs (QWFETs) with a 3D fin geometry, InGaAs
> > for the NFET channel, and strained Germanium for the PFET channel,
> > enabling lower voltage and more energy efficient
> > transistors in 2016, and the rest of the industry will follow suit at the 7nm node.
> >
> > The full article is available at http://www.realworldtech.com/intel-10nm-qwfet/
> >
> > As always, post questions, comments, feedback, flames, etc. here.
> >
> > David
This is a great find - thanks!
> According to Victor Moroz @ Synopsys, there is no Group IV vs III-V combination champion. It
> is a close race with no clear winner, and the best choice depends on your chip specification.
> He thinks that Silicon is still the best channel material, at least for LP mobile devices.
I agree that silicon is best for low leakage (e.g., phones, tablets). He's totally spot on - Generally III-V/Ge doesn't improve leakage, but it's really great at ~0.5V.
> Moroz also concluded that nobody can pull off LP at 0.5V Vdd and that in order to
> have 0.5V Vdd the variability has to go down ~2x which he thinks is a stretch:
>
> http://www.avsusergroups.org/jtg_pdfs/2014_7moroz_Synopsis.pdf
Actually this is pretty consistent with what I've been saying. Silicon will be cointegrated with III-V/Ge, with the latter being used for high performance transistors and silicon for LP (or lower value stuff).
I suspect he might disagree with me on timing, but I think 7nm is within the realm of possibility.
David