III-V Tailored by Taylor?

Article: What's Next for Moore's Law? For Intel, III+V = 10nm QWFETs
By: Joel (joel.hruska.delete@this.gmail.com), April 24, 2015 7:13 am
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on April 24, 2015 3:03 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on April 23, 2015 2:35 pm wrote:
> > Note that Taylor & Co. claim the cost is competitive with FD-SOI (which I doubt, but let's
> > play nice). Nobody is using FD-SOI because of cost reasons. So the cost argument is silly.
>
> I'd say that nobody is using FD-SOI is an exaggeration. Adoption isn't very high (design wins are
> in the low tens AFAIK) but it's not null either; here's a couple of recent news on the topic:
>
> Sony Joins FDSOI Club
>
>
Sony Corp. revealed that the company’s next-generation Global Navigation Satellite System
> (GNSS) chip will use 28-nm Fully Depleted Silicon On Insulator (FDSOI) process.
>
>

> Freescale, Cisco, Ciena Give Nod to FD-SOI
>
>
Freescale, Cisco and Ciena have defied the general skepticism of fully-depleted
> silicon-on-insulator (FD-SOI) by revealing their own experience with the process
> technology, creating expectations that more companies might follow.
>
>


This still seems like very small potatoes relative to the discussions that were had on the topic. I've seen 28nm SOI floated as an alternative to FinFET for at least 3-4 years. Back in 2011 (I think) there was discussion over whether AMD would go to FD-SOI for future iterations of Piledriver or switch to bulk silicon.

I'm not saying that FD-SOI is inferior -- but it certainly seems as though it didn't achieve much critical mass.
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