III-V Tailored by Taylor?

Article: What's Next for Moore's Law? For Intel, III+V = 10nm QWFETs
By: David Kanter (dkanter.delete@this.realworldtech.com), April 24, 2015 2:56 pm
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on April 24, 2015 3:03 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on April 23, 2015 2:35 pm wrote:
> > Note that Taylor & Co. claim the cost is competitive with FD-SOI (which I doubt, but let's
> > play nice). Nobody is using FD-SOI because of cost reasons. So the cost argument is silly.
>
> I'd say that nobody is using FD-SOI is an exaggeration. Adoption isn't very high (design wins are
> in the low tens AFAIK) but it's not null either; here's a couple of recent news on the topic:
>
> Sony Joins FDSOI Club
>
>
Sony Corp. revealed that the company’s next-generation Global Navigation Satellite System
> (GNSS) chip will use 28-nm Fully Depleted Silicon On Insulator (FDSOI) process.
>
>

> Freescale, Cisco, Ciena Give Nod to FD-SOI
>
>
Freescale, Cisco and Ciena have defied the general skepticism of fully-depleted
> silicon-on-insulator (FD-SOI) by revealing their own experience with the process
> technology, creating expectations that more companies might follow.
>
>


FD-SOI has it's place, but it's not going to be a mainstream technology. Cisco is using it because they want low development costs (their volumes are miniscule), and the body bias really helps, as well as avoiding the big tooling needed for FinFETs.

For anyone with low volumes, I think that FD-SOI could be interesting, and for Ciena, it has other benefits (better for optical stuff).

But generally, FD-SOI is a niche, and an expensive one. If your goal is to match FD-SOI on cost...then that's a pretty bad starting point.

David
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