RWT Article: What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETs

Article: What's Next for Moore's Law? For Intel, III+V = 10nm QWFETs
By: Otis (otistd.delete@this.gmail.comd), April 27, 2015 9:24 pm
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on April 22, 2015 11:48 pm wrote:
> Otis (otistd.delete@this.gmail.com) on April 22, 2015 7:48 am wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on April 21, 2015 2:53 pm wrote:

> >The infrastructure
> > for running III-V on 300mm Si in HVM isn't there yet. From and EHS perspective alone, InGaAs or GaAs
> > is a significant headache, not because of As toxicity as
> > you might think, but because of As carcinogenicity-
> > meaning zero exposure is the goal.
>
> How does this compare to the steps taken to isolate any copper from FEOL?

From my perspective it is apples and oranges, but I'm a process guy. Cu kills devices, but As kills people. Which is a flippant way of pointing out that the Cu issue isn't a safety issue, it's a quality (i.e. yield) issue. For those of us that work in that fab that is a lot different from a safety issue where EHS becomes heavily involved and tools and procedures need to be audited and certified. And I imagine industrial hygiene needs to be checked and maintained as well.

>
> >The first III-V on 300mm Si was run in Albany withing the past 2 years
> > and reported. That takes significant effort even in a research
> > Fab, converting an HVM fab to run it regularly
> > will be difficult. For every step with exposed GaAs/InGaAs
> > surface you need to have a tool that is certified
> > to run III-V, and very few of them are. Increased maintenance cost for handing As contaminated parts,
> > etc. is another problem. Frankly it's just not there. Last year UCSB reported the first III-V devices
> > that are competitive with 22nm Si, but those are planar and will need some development to build into a
> > scaled/scalable fin structure.
>
> >Finally, the distinction between QWFETs and FinFETs is not so clear as
> > you make it seem- Intels III-V Tri-Gates which you show, do not have a large band gap barrier isolating
> > the channel surface, as in a traditiona QW, so they are really just TriGate- or TriGate is essentially
> > a QW, depending on how you want to look at it- it's a bit fuzzy.
>
> That's right - there's only a single barrier layer and it's beneath the channel,
> as opposed to the planar example (which also had a different mix of In vs. Ga).

Bulk FinFETs use a punch through stopper, that is essentially a counterdoped layer under the fin- which has the same purposes as the Epi barrier. Intel announced the use of Solid source doping at 14nm for the Punch through stopper- they use doped glass and introduced SiN liners inside the STI to do the integration for N and P type.
>
> > Regarding Ge, there are signicant integration issues with pure Ge, and even high Ge SiGe channels that you
> > seem unaware of or at least don't mention.
>
> >However, Ge is in the fab already (SiGe Souce/Drain) and can be
> > handled easily without the additional infrastructure and re-tooling needed for III-V.
>
> Yes, it's definitely a much easier material to work with.
>
> > Actually the IBM alliance
> > partners have low Ge SiGe channels running in HVM. In any case low Ge SiGe ( Ge) could
> > show up at Intel for 10/7nm. Here is a reasonable set of predictions to counter yours.
>
> Awesome - I'm glad you're willing to step up and make some predictions!
>
> > -Intel will introduce low Ge SiGe channels for PFET only at 10nm or possibly 7nm.
>
> Do you think they will do something to improve NFET performance and keep the beta ratio near 1?

At 22nm the Intel PFET was sitting about 85% of NFET drive current. At 14nm they are equal, and no Ge added. How did that come about? (I think I know the answer from a teardown, but not sure it's public). Basically I think they can design the fins so that the beta ratio is near 1- they are already doing that at 14nm.

>
> > -Intel will introduce a Gate All Around (GAA) stacked nanowire FET structure at 7nm or possibly 5nm
>
> I agree that Intel will likely look at GAA next to improve short channel behavior.

Basic point is that GAA improves N and P both without introducing complex heterointegration, so that will come before high Ge PFET and III-V of any kind. The fins will turn into ~4 nanowires stacked on top of each other.

>
> > -Intel will not use III-V for logic device channels prior to 5nm except possibly as a peripheral
> > device integrated for mobile apps in the MOL or BEOL (not at the transistor level)- personally
> > I seriously doubt III-V will come to logic at all, but certainly not before 5nm.
>
> I think it's quite possible that some classes of devices will never get high mobility materials
> due to cost constraints. Ironically, I see the best fit for high mobility in servers rather than
> mobile. Reducing voltage is a big deal for servers if you can keep constant performance.
>
> David

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RWT Article: What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETsDavid Kanter2015/04/21 02:53 PM
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