How much faster?

Article: What's Next for Moore's Law? For Intel, III+V = 10nm QWFETs
By: rwessel (robertwessel.delete@this.yahoo.com), April 29, 2015 3:00 pm
Room: Moderated Discussions
abraidwood (alistair_braidwood.delete@this.yahoo.co.uk) on April 29, 2015 11:27 am wrote:
> rwessel (robertwessel.delete@this.yahoo.com) on April 29, 2015 11:02 am wrote:
> > Pierre (Boutoukoat.delete@this.yahoo.fr) on April 29, 2015 4:38 am wrote:
> > > >
> > > > In layman's terms ... how much faster does the final device go?
> > > >
> > >
> > > Moore's law is not about speed, it is about #transistors vs. costs. The manufacturer
> > > going from 20 to 10 nm will be able to store 4 times more processors per wafer,
> > > or 4 times more transistor per processor, at ~identical~ costs.
> >
> >
> > Costs have not been decreasing at the historical rate. Things like multi-patterning are driving those up.
>
> Am just thinking out loud and am very hungry & maybe not making sense... but...
>
> Faster could have a bearing on cost though - if you made cores that ran 4x faster for the same power, could
> you have 4x fewer? I know most of the area is not cpu cores, but there are a lot of gpu 'cores' on modern
> chips and if you could make them substantially faster per unit, then you could reduce area & cost?
>
> I know that graphics is easily parallel and a design with many slower, lower powered gpu 'cores'
> has better power characteristics than one with fewer faster, more power hungry ones,


In general, a 2X CPU is always better than two 1X CPUs. Usually substantially better (a few pathological cases give the edge to the dual core configuration). The problem is that increasing single threaded performance has become very difficult, in large part because of the power requirements associated with higher clock speeds. So the hardware guys are building multi-core CPUs, rather than the faster single core CPUs that everyone actually wants, because that's all they *can* do. For EP problems, like graphics acceleration, it's mostly about maximizing the power efficiency (computations per Joule), which enables the largest number of compute units on the device (although some minimum performance requirements exist).
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