By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), July 7, 2015 2:49 am
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on July 6, 2015 12:55 pm wrote:
> adrp+add
> are "optimized" sequences, which I assume means they are fused. (adrp+ldr is not mentioned)
It's not explicit but clearly implied, see page 10:
«
4. In the Cortex®-A57 processor r1p0 and later revisions, sequential ADRP/ADD instruction pairs can be
executed with one-cycle execute latency and four instruction/cycle execution throughput in I0/I1. See
Section 4.14 for more information
»
> adrp+add
> are "optimized" sequences, which I assume means they are fused. (adrp+ldr is not mentioned)
It's not explicit but clearly implied, see page 10:
«
4. In the Cortex®-A57 processor r1p0 and later revisions, sequential ADRP/ADD instruction pairs can be
executed with one-cycle execute latency and four instruction/cycle execution throughput in I0/I1. See
Section 4.14 for more information
»