Linus Torvalds (torvalds.delete@this.linux-foundation.org) on July 6, 2015 3:59 pm wrote:
> Of course, it can be pretty subtle. This is another area where both ARM and PowerPC screwed up their
> memory ordering model. Their ordering rules are actually different for conditional moves and for conditional
> branches. For both ARM and Power, a data dependency between two memory read operations implies an
> ordering (so you don't need to put a read barrier between loading a pointer and loading something
> off the pointer), but a control dependency does not (so you do need to put a memory barrier between
> loading a value and conditionally based on that value loading something else).

Besides the issues mentioned by anon, the memory barrier required for a control dependency
can be avoided by adding an (otherwise spurious) address dependency, e.g.,
and-ing the result of the first load with 0 and or-ing the resulting 0 with the address of
the subsequent load.

This is why the PowerPC and ARM memory models specify things this way.