Sylvain Collange (sylvain.collange.delete.delete@this.this.gmail.com) on July 8, 2015 10:32 am wrote:
> Maynard Handley (name99.delete@this.name99.org) on July 8, 2015 9:46 am wrote:
> > BTW, seeing Andre Seznec's name there, does any commercial
> > processor yet implement a PPM or TAGE-like predictor yet?
>
> I am not aware of any official statement about a commercial TAGE implementation.
>
> But comparing Haswell's performance counters with the output of a TAGE simulator, we observe
> comparable branch misprediction rates on average. (http://hal.inria.fr/hal-01100647/)

Hey, I am already years behind in my reading — stop linking to further interesting reading! ☺

> Incidentally, at ISCA 2012, André received an Intel Research Impact Medal for his "exemplary work
> on high-performance computer micro-architecture, branch prediction and cache architecture, [that]
> has been of tremendous benefit to Intel, the industry, and the academic community as a whole". :)


I am disappointed that very little seems to have been done with skewed associativity. Perhaps with the increased emphasis on energy efficiency, skewed associativity may find some use in the near future.

(If I had the means and motivation to do some actual research, I would be tempted to explore the use of overlaid skewed associativity (which Seznec developed for supporting multiple page sizes in a TLB without capacity issues or CAM overhead) with way-based dueling and different indexing for code and data in a shared cache as well as the interaction of skewed associativity with various forms of way prediction. It seems that there is a lot of scope for research on skewed associativity.)