By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), July 14, 2015 9:01 am
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on July 13, 2015 2:10 pm wrote:
> Linus Torvalds (torvalds.delete@this.linux-foundation.org) on July 13, 2015 1:46 pm wrote:
[snip]
>> And my claim is that
>>
>> (a) weak memory ordering doesn't actually buy you anything but confusion and very
>> subtle bugs despite (and sometimes due to) more complex code to handle it.
[snip]
> I'm not competent to discuss the technical issues, but if the matter is as cut-and-dried
> as you claim, why does it continue? There is nothing to stop ARM saying "part of ARM v8.1a
> is a new TSO memory model". Old code would still work (with the mem barriers appropriately
> NOP'd or close to), and new code would have no (or fewer and weaker) mem barriers.
I am far less competent (not even a programmer), but I would guess that ARM has a greater interest in cache coherent systems with simpler cores (and interconnects) as well as a desire to preserve implementation flexibility (as strongly ordered is a strict subset of weakly ordered). I suspect that for many of the use cases, the performance of barriers is not important, so an implementation could presumably sacrifice performance for lower complexity.
> My argument about this is sociological not technical. I'm just not convinced that "everyone is a
> doodyhead except me" is that likely. I saw what you read about "ARM's decision made sense given where
> they were coming from", and again, that just does not strike me as a compelling argument.
>
> I would have thought the issue is design and validation; but David claimed Andy Glew said these
> were equal for ARM and x86. Seems unlikely to me, but Glew knows a hell of a lot more than me.
> So if design and validation aren't any easier, I imagine ARM must believe that weak ordering gives them
> either lower power and/or more scalability.
Above I proposed (downward) core (and interconnect) implementation scalability as a possibility. I also suspect that ARM's licensing model may also make a weaker consistency model more attractive both in facilitating implementation flexibility and in being able to separate features for licensing (e.g., fast barrier support becomes a premium feature).
> I just don't buy that they're doing it because they all thought
> "we have to go for ideological purity over the dirty pragmatism of those Intel idiots" or "we will never
> in our lives design a CPU more complicated than the A57, so let's optimize the ISA spec for that".
> Linus Torvalds (torvalds.delete@this.linux-foundation.org) on July 13, 2015 1:46 pm wrote:
[snip]
>> And my claim is that
>>
>> (a) weak memory ordering doesn't actually buy you anything but confusion and very
>> subtle bugs despite (and sometimes due to) more complex code to handle it.
[snip]
> I'm not competent to discuss the technical issues, but if the matter is as cut-and-dried
> as you claim, why does it continue? There is nothing to stop ARM saying "part of ARM v8.1a
> is a new TSO memory model". Old code would still work (with the mem barriers appropriately
> NOP'd or close to), and new code would have no (or fewer and weaker) mem barriers.
I am far less competent (not even a programmer), but I would guess that ARM has a greater interest in cache coherent systems with simpler cores (and interconnects) as well as a desire to preserve implementation flexibility (as strongly ordered is a strict subset of weakly ordered). I suspect that for many of the use cases, the performance of barriers is not important, so an implementation could presumably sacrifice performance for lower complexity.
> My argument about this is sociological not technical. I'm just not convinced that "everyone is a
> doodyhead except me" is that likely. I saw what you read about "ARM's decision made sense given where
> they were coming from", and again, that just does not strike me as a compelling argument.
>
> I would have thought the issue is design and validation; but David claimed Andy Glew said these
> were equal for ARM and x86. Seems unlikely to me, but Glew knows a hell of a lot more than me.
> So if design and validation aren't any easier, I imagine ARM must believe that weak ordering gives them
> either lower power and/or more scalability.
Above I proposed (downward) core (and interconnect) implementation scalability as a possibility. I also suspect that ARM's licensing model may also make a weaker consistency model more attractive both in facilitating implementation flexibility and in being able to separate features for licensing (e.g., fast barrier support becomes a premium feature).
> I just don't buy that they're doing it because they all thought
> "we have to go for ideological purity over the dirty pragmatism of those Intel idiots" or "we will never
> in our lives design a CPU more complicated than the A57, so let's optimize the ISA spec for that".
