By: NoSpammer (no.delete@this.spam.com), July 15, 2015 12:50 pm
Room: Moderated Discussions
dmcq (dmcq.delete@this.fano.co.uk) on July 15, 2015 8:04 am wrote:
> I doubt a CPU would want to push it out in random order, but consider the problem in general with weak consistency.
> If there are two memory controllers and the string occupies three lines then the second memory controller might
> be satisfying some requests by another CPU delaying the write of the middle section of the string.
On a weakly ordered CPU it would get down to the details of how writes are buffered and eventually written. If the writes are reordered then of course there will be a mess without fences.
I checked Intel docs again and I read that you need only one additional normal write and it will be ordered after string operation. So if you do a normal write to sync then even string operations before it are not problematic. So the simple way to understand Intel rules is: don't rely on the exact implementation of string writes, but they will be ordered with respect to both previous and later writes.
> I doubt a CPU would want to push it out in random order, but consider the problem in general with weak consistency.
> If there are two memory controllers and the string occupies three lines then the second memory controller might
> be satisfying some requests by another CPU delaying the write of the middle section of the string.
On a weakly ordered CPU it would get down to the details of how writes are buffered and eventually written. If the writes are reordered then of course there will be a mess without fences.
I checked Intel docs again and I read that you need only one additional normal write and it will be ordered after string operation. So if you do a normal write to sync then even string operations before it are not problematic. So the simple way to understand Intel rules is: don't rely on the exact implementation of string writes, but they will be ordered with respect to both previous and later writes.
