anon (anon.delete@this.anon.com) on July 14, 2015 9:37 pm wrote:
>
> At it's most general, looking at system-wide state, this is untrue. Forwarding from the store
> queue means that a write can be seen (from one CPU) and then not be seen (from another).

Hmm. Yes and no.

To some independent observer looking from the outside, what you say is obviously true: the CPU that does a write can do a read and see the value of that write, while another CPU that does a read slightly later still sees the old value.

But that's not that different from relativity, where "before" and "after" sometimes don't have meaning. Two independent observers may not agree on what happened before, and what happened after.

But what does have meaning is causality. In physics, everybody still agrees about the order of two causally related events, even if they might not agree on the order of two non-causally related (independent) events. So within the "light cone" of the events, ordering matters and is well-defined.

And as in physics, so in x86 memory ordering. "before" and "after" are kind of ambiguous things for two events that don't have anything in common. But causality is not.

And the x86 memory ordering is explicitly causal. I'm pretty sure it's one of the documented litmus tests, although I didn't look that up again.

Anyway, causality actually gives "before and after" some meaning. In a way that "an independent outside observer that can bypass the cache coherency and see some absolute physical ordering" does not.

(And as mentioned before, breaking causality also breaks peoples brains. It causes bugs because it violates some of our most strictly held intuitions that we don't even think about, and causes code that looks "obviously correct" to not necessarily actually work right.)

I really think causal consistency is probably the most important memory ordering constraint. I wonder what the weakest memory ordering possible is that is still causally consistent. Somebody must know.

Linus