The POWER4 had the same structure

By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), July 17, 2015 5:20 am
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on July 16, 2015 7:34 am wrote:
> Does anyone know how store buffering was handled in POWER 4, 5, & 7?

I haven't found information about POWER6 and POWER7 but this is from the POWER4 Processor
Introduction and Tuning Guide
:

2.3.7 Store instruction processing

Store instructions are assigned an entry in the SRQ during the issue stage for tracking by the real address of the stored data. The store data queue (SDQ) has 32 double-word entries and receives the data being stored in an entry corresponding to the address entry in the SRQ. Stores are removed from the SRQ and SDQ and the data is written to the L2 once it has been completed and all older stores have been successfully sent to the L2.

Since the nomenclature used is exactly the same as in the POWER8 manual I think we can reasonably expect that all following processors - except maybe for the POWER6 - had essentially the same structure and wrote stores in program order to the coherency point.
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                You don't need isel eitherGabriele Svelto2015/07/08 05:22 AM
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