By: Etienne (etienne_lorrain.delete@this.yahoo.fr), July 17, 2015 6:39 am
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on July 17, 2015 4:51 am wrote:
> Another reasons are more ISA specific.
> For example, IA32/iAMD64 does not have an instruction for either conditional register-indirect branch&link or
> for conditional register-indirect call.
Look for ia32 "bound" instruction, it is a perfect fit but was never used because it is too slow, and it is never used so has never been optimised.
It is obviously predicted not-taken, do not require a bound-failed target register address, and was even supported by some GCC version.
> argument that hardware to speed up bound checks
Even better, hardware to do saturating calculus and end-of-calculus (i.e. delayed) failure report (result register containing NaN) on integers (like for floats) may be even better: not so many error paths to treat.
> Another reasons are more ISA specific.
> For example, IA32/iAMD64 does not have an instruction for either conditional register-indirect branch&link or
> for conditional register-indirect call.
Look for ia32 "bound" instruction, it is a perfect fit but was never used because it is too slow, and it is never used so has never been optimised.
It is obviously predicted not-taken, do not require a bound-failed target register address, and was even supported by some GCC version.
> argument that hardware to speed up bound checks
Even better, hardware to do saturating calculus and end-of-calculus (i.e. delayed) failure report (result register containing NaN) on integers (like for floats) may be even better: not so many error paths to treat.
