By: anon (anon.delete@this.anon.com), July 20, 2015 7:29 am
Room: Moderated Discussions
Konrad Schwarz (konrad.schwarz.delete@this.siemens.com) on July 20, 2015 4:44 am wrote:
> Except that barrier operations are -- at least by default -- global: the store queues of all
> coherent CPUs are drained when a (global) barrier instruction is executed (by one CPU).
Which CPUs and which barrier instructions might those be?
> Except that barrier operations are -- at least by default -- global: the store queues of all
> coherent CPUs are drained when a (global) barrier instruction is executed (by one CPU).
Which CPUs and which barrier instructions might those be?