By: Konrad Schwarz (konrad.schwarz.delete@this.siemens.com), July 21, 2015 12:08 am
Room: Moderated Discussions
anon (anon.delete@this.anon.com) on July 20, 2015 7:29 am wrote:
> Konrad Schwarz (konrad.schwarz.delete@this.siemens.com) on July 20, 2015 4:44 am wrote:
> > Except that barrier operations are -- at least by default -- global: the store queues of all
> > coherent CPUs are drained when a (global) barrier instruction is executed (by one CPU).
>
> Which CPUs and which barrier instructions might those be?
>
I know of Power(PC) and ARM.
> Konrad Schwarz (konrad.schwarz.delete@this.siemens.com) on July 20, 2015 4:44 am wrote:
> > Except that barrier operations are -- at least by default -- global: the store queues of all
> > coherent CPUs are drained when a (global) barrier instruction is executed (by one CPU).
>
> Which CPUs and which barrier instructions might those be?
>
I know of Power(PC) and ARM.