By: Michael S (already5chosen.delete@this.yahoo.com), July 21, 2015 3:11 am
Room: Moderated Discussions
Konrad Schwarz (konrad.schwarz.delete@this.siemens.com) on July 21, 2015 12:08 am wrote:
> anon (anon.delete@this.anon.com) on July 20, 2015 7:29 am wrote:
> > Konrad Schwarz (konrad.schwarz.delete@this.siemens.com) on July 20, 2015 4:44 am wrote:
> > > Except that barrier operations are -- at least by default -- global: the store queues of all
> > > coherent CPUs are drained when a (global) barrier instruction is executed (by one CPU).
> >
> > Which CPUs and which barrier instructions might those be?
> >
>
> I know of Power(PC) and ARM.
Which PowerPC barrier instruction?
isync ? - certainly non-global
eieio ? - does not appear to be global
mbar ? looks like it does not exist on "big" IBM cores. Not sure about "biggish" Freescale cores, like e600. Anyway, programming note suggests that mbar is intended for memory-mapped I/O synchronization rather than SMP synchronization.
sync ? In my copy of docs (PowerISA_v2.07) they list 18 legal forms of sync in m. Which one is global?
> anon (anon.delete@this.anon.com) on July 20, 2015 7:29 am wrote:
> > Konrad Schwarz (konrad.schwarz.delete@this.siemens.com) on July 20, 2015 4:44 am wrote:
> > > Except that barrier operations are -- at least by default -- global: the store queues of all
> > > coherent CPUs are drained when a (global) barrier instruction is executed (by one CPU).
> >
> > Which CPUs and which barrier instructions might those be?
> >
>
> I know of Power(PC) and ARM.
Which PowerPC barrier instruction?
isync ? - certainly non-global
eieio ? - does not appear to be global
mbar ? looks like it does not exist on "big" IBM cores. Not sure about "biggish" Freescale cores, like e600. Anyway, programming note suggests that mbar is intended for memory-mapped I/O synchronization rather than SMP synchronization.
sync ? In my copy of docs (PowerISA_v2.07) they list 18 legal forms of sync in m. Which one is global?