Konrad Schwarz (konrad.schwarz.delete@this.siemens.com) on July 21, 2015 7:36 am wrote:
> anon (anon.delete@this.anon.com) on July 21, 2015 6:22 am wrote:
>
> > I don't believe that is the case for Power. Not sure about ARM, I don't know so much about it.
> >
> > From the Power ISA 2.07 manual, Book II 1.7:
>
> 1.7.1 of 2.07 Book II defines cumulative barriers, and the instruction description of synchronize states
> The ordering done by the memory barrier is cumulative
> (regardless of the E and L values).
>
> This seems to be a tightening over 2.06.
>
> Note that this is all described in Book II. Book I is the ISA of interest to application programmers.
>
> For ARMv7, A3.8.3 Memory barriers:

It appears that we are performing operations on the same data concurrently, but failing to be orderly in what we write here.


>
>

> Data Memory Barrier (DMB)
> The DMB instruction is a data memory barrier. The processor
> that executes the DMB instruction is referred to as the
> executing processor, Pe. The DMB instruction takes the required
> shareability domain and required access types as
> arguments, see Shareability and access limitations on the
> data barrier operations on page A3-150. If the required
> shareability is Full system then the operation applies to all observers within the system.
> A DMB creates two groups of memory accesses, Group A and Group B:
> Group A Contains:
> • All explicit memory accesses of the required access types from observers in the same
> required shareability domain as Pe that are observed by Pe before the DMB instruction. These
> accesses include any accesses of the required access types performed by Pe.
> • All loads of required access types from an observer Px in the same required shareability
> domain as Pe that have been observed by any given different observer, Py, in the same
> required shareability domain as Pe before Py has performed a memory access that is a
> member of Group A.
> Group B Contains:
> • All explicit memory accesses of the required access types by Pe that occur in program order
> after the DMB instruction.
> • All explicit memory accesses of the required access types by any given observer Px in the
> same required shareability domain as Pe that can only occur after Px has observed a store that
> is a member of Group B.
>

Yes, so like Power ISA, I think that's establishing causality with respect to Pe and its memory barrier. I don't think it necessarily requires ordering of observers accesses though, unless they have been observed themselves (i.e., have a causal relationship with the barrier).